A reconfigurable architecture for real-time digital simulation of neurons

Abstract

A major problem in computational neuroscience is that large scale biologically realistic neuron simulations require massive amounts of computing resources, which in turn requires large amounts of power. This poses a significant problem when we look toward a potential future where machines have "silicon brains". In this paper we build on previous VHDL neuron work by building a programmable neuron device housing 116 neurons and 200 synapses to perform realistic, real-time simulations of neuron networks in hardware. This flexible architecture is loaded with the C. elegans locomotion system which demonstrates that the behavior of the programmable architecture is the same as the behavior of the design from previous work.

An Analytical Comparison of Locally-Connected Reconfigurable Neural Network Architectures Using a C. elegans Locomotive Model

“…Since each neuron must drive the bus once per simulated time step, the simulation clock must run much slower to accommodate for the increase in scale. This system is therefore not scalable; however, by ensuring that synapse to synapse connections were performed outside the scope of the wider connection infrastructure, this system achieved measured speed-ups of 20× that of previous models it was compared against [12].…”