A reconfigurable and adaptive routing method for fault-tolerant mesh-based networks-on-chip

Valinataj, Mojtaba; Mohammadi, Siamak; Plosila, Juha; Liljeberg, Pasi; Tenhunen, Hannu

doi:10.1016/j.aeue.2010.09.002

Cited by 45 publications

(35 citation statements)

References 22 publications

(26 reference statements)

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“…The performance estimation of this connection retaining approach is compared with two methods, called Reconfigurable Switch algorithm [13] and Reconfigurable Links algorithm [14]. In the other methods, packets may take unnecessary longer paths to reach destinations.…”

Section: Resultsmentioning

confidence: 99%

“…There are few papers discussed to deal with faults in links [12][13] and routers [11] [14]. Few methods never use virtual channels [9][10][11] [15].…”

Section: Related Workmentioning

confidence: 99%

“…The algorithm [12] tolerate single fault. Another algorithm [14] tolerates two faulty links in the network. DBP [19] approach uses a lightweight approach to maintain the network connectivity among non-faulty routers.…”

Section: Related Workmentioning

confidence: 99%

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Fpga Based Highly Reliable Fault Tolerant Approach for Network on Chip(noc)

.¹

2014

IJRET

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Network on chip is an interconnection between several processing elements and routers. There are several possibilities for the occurrence of faults within the network. These faults degrade the performance of the network. In order to increase the performance several fault tolerant methods has been used. They involve themselves in rerouting and hence take longer paths. To make the path shorter, the router architecture has to be modified. The introduction of minimal routing algorithm for faults in the network increases the overall performance of the network. When we use the algorithm, it takes shortest path regardless of the presence of faults. The proposed algorithm is much simpler than the previous existing algorithm. It provides link among the surviving routers in the network. It proves to be more efficient even in the presence of multiple faults. It has the ability to connect the routers both horizontally and orthogonally even in the presence of faults. It has reduced delay over the network. It has proved to be more reliable of 99.5% when multiple faults are found in the network. It can be used in 4x4 mesh topology with six faulty routers to analyse the reliability of network. It also helps to estimate the various parameters such as reliability, latency, speed, area and power.

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Section: Resultsmentioning

confidence: 99%

“…There are few papers discussed to deal with faults in links [12][13] and routers [11] [14]. Few methods never use virtual channels [9][10][11] [15].…”

Section: Related Workmentioning

confidence: 99%

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Fpga Based Highly Reliable Fault Tolerant Approach for Network on Chip(noc)

.¹

2014

IJRET

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“…At present, a method has been proposed to use virtual channel [5] aimed to ensure the deadlock-free property of fault-tolerant routing, which can send data package by employing virtual channel according to a certain path in a defective routing or in a defective area. However, low cost routers on which network on chip depend should be offered to this approach, which needs additional system overhead.…”

Section: Introductionmentioning

confidence: 99%

The reconfigurable fault tolerance routing algorithm in mesh topology structure

Hua

Yong

et al. 2014

10th International Conference on Wireless Communications, Networking and Mobile Computing (WiCOM 2014)

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The reconfigurable fault-tolerant routing algorithm in Mesh Topology Structure which belongs the field of net work on chip has a feature, which is that the method achieves fault tolerance by using north last turning model and less-stored routing list. The reconfigurable fault toler ance routing algorithm has a series of merits: practical convenience, high fault-tolerance performance, low cost and little hardware expense. Moreover, if there is not any fault, the XY routing algorithm with application certainty could ensure reliable transmission of information, which divides a router into two parts including fringe nodes and middle nodes. But, in the case of faults, information that comes from middle nodes should be transmitted according to north last turning model and information derive from fringe nodes should be conveyed by routing list in order to efficient transmission. Networks-on-chip (NoC) is a struc ture with redundancy feature. That is to say, there are many path ways from the source node to target node, which provides us with researching condition of fault tol erance routing algorithm. The algorithm is a kind of low cost, simple structure, low power consumption, a recon figurable fault-tolerant routing algorithm for small memory.

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“…Virtual channels are mainly used in the faulttolerant routing method for avoiding deadlock [1], improving performance and tolerating faults, but they introduce the additional area and increase the complex control logic of the router. Another fault-tolerant routing method without virtual channels avoids deadlock by using turn model [2], decreasing hardware costs, but it lowers performance because of less adaptivity.…”

Section: Introductionmentioning

confidence: 99%

Low-Cost Adaptive and Fault-Tolerant Routing Method for 2D Network-on-Chip

Xie

Xin

Yang

2017

IEICE Trans. Inf. & Syst.

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SUMMARY This letter presents a Preferable Mad-y (PMad-y) turn model and Low-cost Adaptive and Fault-tolerant Routing (LAFR) method that use one and two virtual channels along the X and Y dimensions for 2D mesh Network-on-Chip (NoC). Applying PMad-y rules and using the link status of neighbor routers within 2-hops, LAFR can tolerate multiple faulty links and routers in more complicated faulty situations and impose the reliability of network without losing the performance of network. Simulation results show that LAFR achieves better saturation throughput (0.98% on average) than those of other fault-tolerant routing methods and maintains high reliability of more than 99.56% on average. For achieving 100% reliability of network, a Preferable LAFR (PLAFR) is proposed.

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A reconfigurable and adaptive routing method for fault-tolerant mesh-based networks-on-chip

Cited by 45 publications

References 22 publications

Fpga Based Highly Reliable Fault Tolerant Approach for Network on Chip(noc)

Fpga Based Highly Reliable Fault Tolerant Approach for Network on Chip(noc)

The reconfigurable fault tolerance routing algorithm in mesh topology structure

Low-Cost Adaptive and Fault-Tolerant Routing Method for 2D Network-on-Chip

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