A reconfigurable 2-D IDCT architecture for HEVC encoder/decoder

Kilany, Ahmed; Abdelrasoul, Maher; Shalaby, Ahmed; Sayed, Mohammed S.

doi:10.1109/icm.2015.7438033

Cited by 3 publications

(5 citation statements)

References 7 publications

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“…The high-performance core associated with 90-nm technology is able to support 3840 × 2160@30 fps; however, the structure of the multiplexer reduces the operating frequency by half [12]. In [20], a new reconfigurable pipelined architecture for IDCT is introduced. This approach was shown to greatly reduce circuit area and cost.…”

Section: Comparison and Discussionmentioning

confidence: 99%

“…The architectures support real-time processing of 8 K ultrahigh-definition video sequences at 64 and 26 fps, respectively, and show high throughput and low gate count implementations. In [20], a new reconfigurable pipelined architecture for IDCT is introduced. This architecture implemented on TSMC 65 nm runs at a clock frequency of 500 MHz and achieves throughput of 1990 megapixel/s.…”

Section: Comparison and Discussionmentioning

confidence: 99%

“…The design in [11] utilizes about two computation paths to reach high throughput rate; however, large area cost resulting in the hardware efficiency is only 2.21. The high throughput rate in [19][20][21] was due to high operation frequency for [19,20] and high processing rate [21]. The results in [21] is only 1-D architecture; thus, high hardware efficiency can be achieved.…”

Section: Comparison and Discussionmentioning

confidence: 99%

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High‐throughput IDCT architecture for high‐efficiency video coding (HEVC)

Chen

2017

Circuit Theory & Apps

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This paper presents a hardware design capable of supporting high-efficiency video coding inverse discrete cosine transform (IDCT) with a 32 × 32 transform unit size, using a single 1-D IDCT core with transpose memory to reduce costs. The proposed 1-D IDCT core employs 16 computation paths for high throughput and is implemented using distributed arithmetic to facilitate the sharing of hardware resources. The proposed 1-D IDCT is capable of calculating 1-D and 2-D data simultaneously along 32 parallel paths. When implemented using Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm CMOS technology, the proposed 2-D transform core provides throughput of 6.4 gigapixels/s with a gate count of 335 k. The results show that a superior hardware efficiency can be achieved in the proposed 32-point IDCT core compared with the existing works.

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Section: Comparison and Discussionmentioning

confidence: 99%

Section: Comparison and Discussionmentioning

confidence: 99%

Section: Comparison and Discussionmentioning

confidence: 99%

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High‐throughput IDCT architecture for high‐efficiency video coding (HEVC)

Chen

2017

Circuit Theory & Apps

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“…Therefore, there are a few publications detailing the hardware implementations of the DCT transforms to fulfil the requirements of the standard. Most of the existing works focus on implementing either DCT circuit [7][8][9][10][11][12][13] or IDCT circuit [14][15][16][17][18]. In [7] three flexible architectures were proposed to perform one-dimensional (1D)-DCT operation for any DCT size focusing on the reusability and flexibility that allow one design to do more than one function.…”

Section: Related Workmentioning

confidence: 99%

“…In [17], a flexible architecture for HEVC IDCT, based on the division of transform into fixed‐size blocks, was proposed. In [18] a reconfigurable IDCT architecture is proposed based on matrix multiplication reduction and process control circuit for the reconfiguration.…”

Section: Related Workmentioning

confidence: 99%

Real‐time unified architecture for forward/inverse discrete cosine transform in high efficiency video coding

Abdelrasoul

Sayed

Goulart

2017

IET Circuits, Devices & Systems

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In High Efficiency Video Coding (HEVC) standard, higher video resolutions employ larger integer Discrete Cosine Transform (DCT)/inverse DCT (IDCT) block sizes. In this study, the authors propose two high-throughput unified DCT/IDCT architectures. The proposed architectures can process variable DCT/IDCT block sizes according to the HEVC standard. The proposed architectures were prototyped on TSMC 65 nm CMOS technology. The prototyping results show that the two unified architectures have throughput of 15.24 and 16.03 Gsps, respectively, and they can encode video sequences with resolutions up to 8 K at 120 fps and decode the same resolution at 240 fps using only one circuit for both DCT and IDCT.

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