A Realizable Digital Bubble Sorting SAR ADC Calibration Technology

Fan, Hua; Wang, Yunan; Wu, Xianguo

doi:10.1109/icicdt51558.2021.9626536

Cited by 2 publications

(1 citation statement)

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“…In this work, segmentation in the capacitors array was used as one solution to the chip area issue [6,16]. Nevertheless, a segmented architecture increases sensitivity to the capacitors' mismatch; thus, an additional digital calibration algorithm is necessary [16][17][18][19][20][21][22]. Many digital calibration architectures are very efficient; however, they increase both the circuit complexity and the total area.…”

Section: Introductionmentioning

confidence: 99%

Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm

Bontems

Dzahini

2023

Chips

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This paper presents a design methodology for a low-power, low-chip-area, and high-resolution successive approximations register (SAR) analog-to-digital converter (ADC). The proposed method includes a segmented capacitive DAC (C-DAC) to reduce the power consumption and the total area. An embedded self-calibration algorithm based on a set of trimming capacitors was applied alongside a dynamic element matching (DEM) procedure to control the inherent linearity issues caused by the process mismatch. The SAR ADC and each additional algorithm were modeled in MATLAB to show their efficiency. Finally, a simple methodology was developed to allow for the fast estimation of signal-to-noise ratios (SNRs) without any FFT calculation.

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