A Real-Time Virtio-Based Framework for Predictable Inter-VM Communication

Schwaricke, Gero; Tabish, Rohan; Pellizzoni, Rodolfo; Mancuso, Renato; Bastoni, Andrea; Zuepke, Alexander; Caccamo, Marco

doi:10.1109/rtss52674.2021.00015

Cited by 8 publications

(7 citation statements)

References 37 publications

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“…Memory bandwidth is monitored using performance counters. Depending on platforms capabilities, implementations of MemGuard have used PMCs from cores' PMUs (Yun et al 2016;Schwaericke et al 2021) or from the DRAM memory controller (Sohal et al 2020;Saeed et al 2022). Since overutilization of memory controllers is detrimental to predictability (Sohal et al 2020), hard realtime systems dimension the memory budget allowed for regulated cores using the principle of maximum sustainable bandwidth.…”

Section: Background and Motivationmentioning

confidence: 99%

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MemPol: polling-based microsecond-scale per-core memory bandwidth regulation

Zuepke,

Bastoni,

Chen

et al. 2024

Real-Time Syst

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In today’s multiprocessor systems-on-a-chip, the shared memory subsystem is a known source of temporal interference. The problem causes logically independent cores to affect each other’s performance, leading to pessimistic worst-case execution time analysis. Memory regulation via throttling is one of the most practical techniques to mitigate interference. Traditional regulation schemes rely on a combination of timer and performance counter interrupts to be delivered and processed on the same cores running real-time workload. Unfortunately, to prevent excessive overhead, regulation can only be enforced at a millisecond-scale granularity. In this work, we present a novel regulation mechanism from outside the cores that monitors performance counters for the application core’s activity in main memory at a microsecond scale. The approach is fully transparent to the applications on the cores, and can be implemented using widely available on-chip debug facilities. The presented mechanism also allows more complex composition of metrics to enact load-aware regulation. For instance, it allows redistributing unused bandwidth between cores while keeping the overall memory bandwidth of all cores below a given threshold. We implement our approach on a host of embedded platforms and conduct an in-depth evaluation on the Xilinx Zynq UltraScale+ ZCU102, NXP i.MX8M and NXP S32G2 platforms using the San Diego Vision Benchmark Suite.

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Section: Background and Motivationmentioning

confidence: 99%

“…5). When DRAM controller performance counters are not available, determining this value requires know-how of the target platform and non-trivial experimental setups (Serrano-Cases et al 2021;Schwaericke et al 2021).…”

Section: Background and Motivationmentioning

confidence: 99%

MemPol: polling-based microsecond-scale per-core memory bandwidth regulation

Zuepke,

Bastoni,

Chen

et al. 2024

Real-Time Syst

Self Cite

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“…Mergendahl et al [23] studied the timing-related "Thundering Herd Attack" to synchronous IPC and budget management mechanisms, targeting the seL4µ-kernel. Other works targeted inter-process communication by studying communication mechanisms and paradigms [24]- [28], while other proposals come from the context of hypervisors [29,30] and separation kernels [31]- [34].…”

Section: Related Workmentioning

confidence: 99%

On the QNX IPC: Assessing Predictability for Local and Distributed Real-Time Systems

Becker

Dasari

Casini

2023

2023 IEEE 29th Real-Time and Embedded Technology and Applications Symposium (RTAS)

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With the advent of massively distributed applications such as those required by the IoT-to-Edge-to-Cloud compute continuum (i.e., automotive, smart agriculture, smart manufacturing, and more), real-time communication mechanisms allowing physically distributed nodes to seamlessly communicate as if they were running on the same host acquired noteworthy importance. To this end, the synchronous inter-process communication (IPC) mechanism provided by the QNX operating system (OS) is a promising candidate, as it allows using the application programming interface for communicating both on a single-and multi-node setting. Furthermore, it provides priority and partition inheritance mechanisms to improve predictability when working with the Adaptive Partitioning Scheduler (APS), a reservationbased scheduler provided by the QNX OS. This paper explores the behavior of the QNX synchronous message-passing (SyncMP) IPC with an extensive set of experiments, using them to formalize its behavior and model it from a real-time perspective. Then, it provides a response-time analysis for client-server applications based on the QNX SyncMP building upon self-suspending task theory. Finally, we evaluate the analysis on an application based on the WATERS 2019 Challenge by Bosch.

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“…Another work presented a framework to limit the traffic introduced in the I/O bus by I/O peripherals [36]. Schwaricke et al [37] leverage virtio to implement an interdomain communication mechanism, where a DMA handles inter-VM data transfers, but without targeting I/O virtualization. As in our proposal, [37] uses the QoS-400 regulators, but with a different objective, i.e., regulating the memory interference generated by DMA-based inter-VM data transfers.…”

Section: Related Workmentioning

confidence: 99%

“…Schwaricke et al [37] leverage virtio to implement an interdomain communication mechanism, where a DMA handles inter-VM data transfers, but without targeting I/O virtualization. As in our proposal, [37] uses the QoS-400 regulators, but with a different objective, i.e., regulating the memory interference generated by DMA-based inter-VM data transfers. Richter et al [38] implemented a scheduling mechanism for mitigating the interference generated by malicious VMs using the SRIO-V technology (not present in the Ultrascale+), and without considering real-time requirements and I/O-related memory contention.…”

Section: Related Workmentioning

confidence: 99%

An I/O Virtualization Framework With I/O-Related Memory Contention Control for Real-Time Systems

Borgioli

Zini

Casini

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Modern applications are often characterized by a tight interaction with I/O devices. At the same time, many application domains are also facing a shift towards an integrated approach where multiple applications with mixed levels of safety and security need to co-exist on top of a shared hardware platform, which is typically managed by a hypervisor. This gives rise to the need for a predictable mechanism allowing multiple virtual machines to share I/O devices, while at the same time controlling contention delays when they access global memory.To deal with these shortcomings, this paper proposes an I/O virtualization framework providing support for controlling the I/O-related memory contention by leveraging the ARM QoS-400 regulators. Extensive experiments are performed to compare the proposed solution with the Xen hypervisor, showing improvements up to 8x when controlling the I/O-related memory contention.

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A Real-Time Virtio-Based Framework for Predictable Inter-VM Communication

Cited by 8 publications

References 37 publications

MemPol: polling-based microsecond-scale per-core memory bandwidth regulation

MemPol: polling-based microsecond-scale per-core memory bandwidth regulation

On the QNX IPC: Assessing Predictability for Local and Distributed Real-Time Systems

An I/O Virtualization Framework With I/O-Related Memory Contention Control for Real-Time Systems

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