A real-time TMS320C40 based parallel system for high rate digital signal processing

Chen, D.C.-C.; Price, R. H.

doi:10.1109/icassp.1991.150549

Cited by 6 publications

(2 citation statements)

References 2 publications

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“…Its external data and address buses can support a shared massive memory and highspeed single-cycle transfer [12][13][14]. The DSP has a high-performance CPU and a DMA coprocessor capable of 275 MOPS and 320 Mbytes/ sec data throughput.…”

Section: The Design Of the Dsp Boardmentioning

confidence: 99%

A Digital Signal Processor For Image Recovery Applications

Ping¹,

Mou²,

Unbehauen³

1994

Frequenz

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In this paper we describe a digital signal processor using TMS320C40 for image recovery applications. The ability for large-size 2-D FFT is a key consideration in the design. By using the vector radix technique, the FFT of size 256 256 may be executed in 190ms by utilizing two C40 chips. A software simulation has been done to verify the design.Übersicht: In der vorliegenden Arbeit wird ein auf TMS320C40-Chips basierender Signalprozessor für Anwendungen zur Bildwiederherstellung beschrieben. Die Fähigkeit zur Bewältigung der zweidimensionalen schnellen Fourier-Transformation (FFT) auch im Fall großer Datensätze bildet den Entwurfsschlüssel. Unter Verwendung der Vektor-Radix-Technik läßt sich die FFT von der Größe 256 256 in 190 ms mit Hilfe von zwei C40-Chips durchführen. Zur Verifikation des Entwurfs wurde eine Computersimulation durchgeführt.Für die Dokumentation: Digitaler Signalprozessor / Bildwiederherstellung / TMS320C40 Prozessor · Vektor-Radix FFT

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Section: The Design Of the Dsp Boardmentioning

confidence: 99%

A Digital Signal Processor For Image Recovery Applications

Ping¹,

Mou²,

Unbehauen³

1994

Frequenz

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show abstract

“…A parallel processing network using these processors has previously been developed [13], but does not have a fault-tolerant ability. Our mesh will improve on this network by increasing the level of parallelism and by adding fault tolerance in the form of spare processors.…”

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confidence: 99%

Fault-Tolerant Recursive Least-Squares Computations on a Mesh-Connected Parallel Processor

Zomaya¹,

Yates

Olariu

2002

Journal of Parallel and Distributed Computing

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Parallel VLSI architectures for real-time kinematics of redundant robots

Walker¹,

Cavallaro²

[1993] Proceedings IEEE International Conference on Robotics and Automation

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Abstract. We describe new architectures for the efficient computation of redundant manipulator kinematics (direct and inverse). By calculating the core of the problem in hardware, we can make full use of the redundancy by implementing more complex self-motion algorithms. A key component of our architecture is the calculation in the VLSI hardware of the Singular Value Decomposition of the manipulator Jacobian. Recent advances in VLSI have allowed the mapping of complex algorithms to hardware using systolic arrays with advanced computer arithmetic algorithms, such as the coordinate rotation (CORDIC) algorithms. We use CORDIC arithmetic in the novel design of our special-purpose VLSI array, which is used in computation of the Direct Kinematics Solution (DKS), the manipulator Jacobian, as well as the Jacobian Pseudoinverse. Application-specific (subtask-dependent) portions of the inverse kinematics are handled in parallel by a DSP processor which interfaces with the custom hardware and the host machine. The architecture and algorithm development is valid for general redundant manipulators and a wide range of processors currently available and under development commercially.

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A real-time TMS320C40 based parallel system for high rate digital signal processing

Cited by 6 publications

References 2 publications

A Digital Signal Processor For Image Recovery Applications

A Digital Signal Processor For Image Recovery Applications

Fault-Tolerant Recursive Least-Squares Computations on a Mesh-Connected Parallel Processor

Parallel VLSI architectures for real-time kinematics of redundant robots

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