A real-time parallel scalable video encoder for multimedia streaming systems

Jian, Guo-An; Lee, Jui-Sheng; Tan, Kheng-Joo; Chen, Peng‐Sheng; Guo, Jiun-In

doi:10.1109/vldi-dat.2013.6533845

Cited by 2 publications

(1 citation statement)

References 6 publications

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“…Representative examples of important computation-intensive algorithms that greatly benefit from parallelization and performance optimization can be found in the field of multimedia processing [Jian et al 2013;Ali et al 2014]. Several researchers have addressed their effort toward some of these algorithms in the past years [Chen et al 2012;Ghodhbani et al 2014].…”

Section: Introductionmentioning

confidence: 99%

Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices

Beretta

Rana

Akın

et al. 2016

ACM Trans. Embed. Comput. Syst.

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The performance and the efficiency of recent computing platforms have been deeply influenced by the widespread adoption of hardware accelerators, such as graphics processing units (GPUs) or fieldprogrammable gate arrays (FPGAs), which are often employed to support the tasks of general-purpose processors (GPPs). One of the main advantages of these accelerators over their sequential counterparts (GPPs) is their ability to perform massive parallel computation. However, to exploit this competitive edge, it is necessary to extract the parallelism from the target algorithm to be executed, which generally is a very challenging task.This concept is demonstrated, for instance, by the poor performance achieved on relevant multimedia algorithms, such as Chambolle, which is a well-known algorithm employed for the optical flow estimation. The implementations of this algorithm that can be found in the state of the art are generally based on GPUs but barely improve the performance that can be obtained with a powerful GPP. In this article, we propose a novel approach to extract the parallelism from computation-intensive multimedia algorithms, which includes an analysis of their dependency schema and an assessment of their data reuse. We then perform a thorough analysis of the Chambolle algorithm, providing a formal proof of its inner data dependencies and locality properties. Then, we exploit the considerations drawn from this analysis by proposing an architectural template that takes advantage of the fine-grained parallelism of FPGA devices. Moreover, since the proposed template can be instantiated with different parameters, we also propose a design metric, the expansion rate, to help the designer in the estimation of the efficiency and performance of the different instances, making it possible to select the right one before the implementation phase. We finally show, by means of experimental results, how the proposed analysis and parallelization approach leads to the design of efficient and highperformance FPGA-based implementations that are orders of magnitude faster than the state-of-the-art ones.

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Section: Introductionmentioning

confidence: 99%

Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices

Beretta

Rana

Akın

et al. 2016

ACM Trans. Embed. Comput. Syst.

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A parallel H.264/SVC encoder for high definition video conferencing

Sanz-Rodríguez

Alvarez-Mesa

Mayer

et al. 2015

Signal Processing: Image Communication

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In this paper we present a video encoder specially developed and configured for high definition (HD) video conferencing. This video encoder brings together the following three requirements: H.264/Scalable Video Coding (SVC), parallel encoding on multicore platforms, and parallel-friendly rate control. With the first requirement, a minimum quality of service to every end-user receiver over Internet Protocol networks is guaranteed. With the second one, real-time execution is accomplished and, for this purpose, slice-level parallelism, for the main encoding loop, and block-level parallelism, for the upsampling and interpolation filtering processes, are combined. With the third one, a proper HD video content delivery under certain bit rate and end-to-end delay constraints is ensured. The experimental results prove that the proposed H.264/SVC video encoder is able to operate in real time over a wide range of target bit rates at the expense of reasonable losses in rate-distortion efficiency due to the frame partitioning into slices

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A real-time parallel scalable video encoder for multimedia streaming systems

Cited by 2 publications

References 6 publications

Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices

Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices

A parallel H.264/SVC encoder for high definition video conferencing

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