A Real-Time Flexible Telecommunication Decoding Architecture Using FPGA Partial Reconfiguration

Ma, Longyu; Sham, Chiu-Wing; Sun, Jing; Tenorio, Raul Valencia

doi:10.1109/tcsii.2019.2953700

Cited by 11 publications

(7 citation statements)

References 14 publications

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“…In addition to each of the QC-LDPC decoders, the overhead caused by DPR is also shown in Table 3. In order to meet the DPR's requirements, what we implement includes but is not limited to a lightweight soft core microprocessor to control the DPR workflow, buffers, such as FIFOs, around decoders and memory controllers, which are standing on [40]. Dynamic power consumption of both decoders and DPR modules are also displayed individually.…”

Section: Fpga Implementation Resultsmentioning

confidence: 99%

“…The scheduling mechanism for which the QC-LDPC codes should be activated on the FPGA is based on Dynamic Partial Reconfiguration [40]. DPR is a circuit-level FPGA technology, allowing users to set a dynamic partition and upload a configuration bit file to that partition without influencing other circuits on the FPGA.…”

Section: F Multi-mode Implementation Using Dynamic Partial Reconfigurationmentioning

confidence: 99%

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An Effective Multi-Mode Iris Authentication System on a Microprocessor-FPGA Heterogeneous Platform With QC-LDPC Codes

Sham

et al. 2021

IEEE Access

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With the emergence and popularity of iris biometrics, there are increasing concerns regarding the feasibility of iris authentication systems and their corresponding variability reduction methods. The former issues are typically addressed by optimizing key factors, such as iris size, image quality and acquisition wavelength. As for the latter, introducing error correction codes to reduce intra-user variability in the enrolled identifiers becomes novelly promising. This paper proposes a conventional iris authentication system and a hardware-friendly QC-LDPC error correction code scheme on a microprocessor-FPGA platform. Different QC-LDPC codes in IEEE 802.16e were analyzed and selected. Suitable codes were applied, followed by the evaluation experiments. The proposed design achieves a competitive result with up to 0.20% EER and 0.50% ZeroFAR on the CASIA-IrisV4-Syn database. Cryptographic keys with lengths of up to 288 bits can also be generated and recovered. Such a device can be potentially used for applications such as an access control system in high-security areas, identity verification at the borders, biometric cryptography and related authentication scenarios.

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Section: Fpga Implementation Resultsmentioning

confidence: 99%

Section: F Multi-mode Implementation Using Dynamic Partial Reconfigurationmentioning

confidence: 99%

An Effective Multi-Mode Iris Authentication System on a Microprocessor-FPGA Heterogeneous Platform With QC-LDPC Codes

Sham

et al. 2021

IEEE Access

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“…FPGA Dynamic Partial Reconfiguration derives from [41]. It provides a circuit-level real-time flexible decoder architecture.…”

Section: Fpga Dynamic Partial Reconfiguration and Multiple Decodersmentioning

confidence: 99%

“…We implement three QC-LDPC decoders onto one partition of Programmable Logic instead of three partitions. The method is based on [41].In terms of real-time switching, the upload size of QC-LDPC decoder bitstream file is 375KB and it takes 1.75ms to change the whole partition of circuit in order to switch different QC-LDPC decoders.…”

Section: B Resource Analysismentioning

confidence: 99%

An Embedded Iris Recognition System Optimization using Dynamically ReconfigurableDecoder with LDPC Codes

Sham

et al. 2021

Preprint

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Extracting and analyzing iris textures for biometric recognition has been extensively studied. As the transition of iris recognition from lab technology to nationscale applications, most systems are facing high complexity in either time or space, leading to unfitness for embedded devices. In this paper, the proposed design includes a minimal set of computer vision modules and multi-mode QC-LDPC decoder which can alleviate variability and noise caused by iris acquisition and follow-up process. Several classes of QC-LDPC code from IEEE 802.16 are tested for the validity of accuracy improvement. Some of the codes mentioned above are used for further QC-LDPC decoder quantization, validation and comparison to each other. We show that we can apply Dynamic Partial Reconfiguration technology to implement the multi-mode QC-LDPC decoder for the iris recognition system. The results show that the implementation is power-efficient and good for edge applications.

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“…In most cases, the hardware has the characteristic that only the necessary parts are partially activated. Therefore, if only the necessary hardware can be implemented in real time, the system will benefit greatly in terms of hardware resources and power [14][15][16].…”

Section: Introductionmentioning

confidence: 99%

An Efficient On-Demand Hardware Replacement Platform for Metamorphic Functional Processing in Edge-Centric IoT Applications

Moon

Park

2021

Electronics

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The paradigm of Internet-of-things (IoT) systems is changing from a cloud-based system to an edge-based system. These changes were able to solve the delay caused by the rapid concentration of data in the communication network, the delay caused by the lack of server computing capacity, and the security issues that occur in the data communication process. However, edge-based IoT systems performance was insufficient to process large numbers of data due to limited power supply, fixed hardware functions, and limited hardware resources. To improve their performance, application-specific hardware can be installed in edge devices, but performance cannot be improved except for specific applications due to a fixed function of an application-specific hardware. This paper introduces an edge-centric metamorphic IoT (mIoT) platform that can use various hardware modules through on-demand partial reconfiguration, despite the limited hardware resources of edge devices. In addition, this paper introduces an RISC-V based metamorphic IoT processor (mIoTP) with reconfigurable peripheral modules. We experimented to prove that the proposed structure can reduce the server access of edges and can be applied to a large-scale IoT system. Experiments were conducted in a single-edge environment and a large-scale environment combining one physical edge and 99 virtual edges. According to the experimental results, the edge-centric mIoT platform that executes the reconfiguration prediction algorithm at the edge was able to reduce the number of server accesses by up to 82.2% compared to our previous study in which the prediction process was executed at the server. Furthermore, we confirmed that there is no additional reconfiguration time overhead even for the large IoT systems.

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A Real-Time Flexible Telecommunication Decoding Architecture Using FPGA Partial Reconfiguration

Cited by 11 publications

References 14 publications

An Effective Multi-Mode Iris Authentication System on a Microprocessor-FPGA Heterogeneous Platform With QC-LDPC Codes

An Effective Multi-Mode Iris Authentication System on a Microprocessor-FPGA Heterogeneous Platform With QC-LDPC Codes

An Embedded Iris Recognition System Optimization using Dynamically ReconfigurableDecoder with LDPC Codes

An Efficient On-Demand Hardware Replacement Platform for Metamorphic Functional Processing in Edge-Centric IoT Applications

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