A Real-Time Cache Side-Channel Attack Detection System on RISC-V Out-of-Order Processor

Abstract

Computer designers have included techniques such as speculative execution and caching to optimize speed and performance. Unfortunately, they could be exploited by the recently discovered cache-side channel attack, spectre. The purpose of this research is to resolve this problem on the open-source RISC-V architecture. Previously, software mitigation techniques and hardware modifications have been investigated on Intel or ARM system to address these issues. However, they are either difficult to implement or have resulted in a significant loss of performance. This work presents a real-time detection approach for cache side-channel attacks such as spectre on the RISC-V processor. By monitoring the CPU's cache activity with Hardware Performance Counters and analyzing the gathered data with a neural network, we extend previous researches in the field of cache side-channel identification. Since cache side-channels frequently result in a significantly altered cache usage pattern, the proposed multi-layer perceptron network can detect an attack event with an accuracy greater than 99% in our test environment with low performance overhead. This is the first time, to our knowledge, that a spectre attack on the RISC-V architecture has been detected in run-time via hardware events and machine learning.

Decentralized Blockchain Network for Resisting Side-Channel Attacks in Mobility-Based IoT

“…The security model presented by Kwon et al [24] used a deep learning approach to identify the presence of side-channel attacks that are non-profiled. The work carried out by Le et al [25] presents a security model for resisting cache attacks using a neural network. The adoption of a convolution neural network is reported in the work of Mukhtar et al [26] towards addressing dual problems of side-channel attack and dimensional reduction.…”

“…(iii) The proposed scheme facilitates the verification of adjacent nodes as well as all other actors in a non-iterative way, which acts as a dual layer of security and increases the frequency of authentication suitable for an extensive dynamic network, unlike the existing approaches , which assess only single target nodes. iv) The proposed scheme is capable of resisting differential fault attacks, power-based attacks, timing attacks and cache attacks, which opens up many opportunities for fighting multiple variants of side-channel attacks, whereas existing approaches [24][25][26][27][28][29][30][31][32][33][34][35][36][37][38] are reported to resist only singular forms of attack.…”

Performance Evaluation of RISC-V Microcontroller System on FPGA: A Study of the NEORV32 Core

“…It is an open-source ISA compared to other closed-source ISAs such as ARM and x86 [3]. Because of RISC-V openness, it has gained widespread adoption and support, encouraging collaborative work by various communities such as research, education, and industry players [4]. Because of its adaptability and support, RISC-V has emerged as a good choice for various applications, particularly in the Internet of Things (IoT) domain [3].…”