2021 IEEE International Symposium on Circuits and Systems (ISCAS) 2021
DOI: 10.1109/iscas51556.2021.9401090
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A Readout Circuit with Current-Compensation-Based Extended-Counting ADC for 1024×768 Diode Uncooled Infrared Imagers

Abstract: This paper presents a low-power readout circuit with 14-bit column-level extended-counting ADC for 17 -pitch × silicon diode uncooled infrared imagers. The ADC's coarse conversion adopts a current-mode DAC to feedback charge into a CTIA-based integrator during integration and the fine conversion is implemented by a SAR ADC after integration. A current self-compensator and a modified DAC are proposed to reduce more than 50% power of the overall integrator compared with conventional structure. The × readout circ… Show more

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Cited by 2 publications
(3 citation statements)
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“…To meet these requirements, the integrated analog-todigital converter (ADC) plays a key role. In recent years, the extended counting (EC) ADC has been developed as an excellent candidate among various kinds of the ADC solutions for large-scale sensor array ROICs [14][15][16][17][18]. Compared with other ADC types such as successive approximate register (SAR) ADC, delta-sigma (Δ-Σ) ADC, and SS-ADC, EC-ADC achieves a good balance between bit-depth, conversion speed, and area.…”
Section: Introductionmentioning
confidence: 99%
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“…To meet these requirements, the integrated analog-todigital converter (ADC) plays a key role. In recent years, the extended counting (EC) ADC has been developed as an excellent candidate among various kinds of the ADC solutions for large-scale sensor array ROICs [14][15][16][17][18]. Compared with other ADC types such as successive approximate register (SAR) ADC, delta-sigma (Δ-Σ) ADC, and SS-ADC, EC-ADC achieves a good balance between bit-depth, conversion speed, and area.…”
Section: Introductionmentioning
confidence: 99%
“…In [15], a folded cascode operational amplifier (op-amp) with gain boosting is adopted to improve the linearity of the CTIA, while the power consumption is too high for large-scale sensor array application. In [16], a current compensation technique is proposed to provide compensation current during the FI period, thus easing the power budget. But an extra high frequency clock is introduced which will generate jitter noise and increase design complexity and digital crosstalk.…”
Section: Introductionmentioning
confidence: 99%
“…However, the limited nonlinear range of operational amplifiers severely restricts the compensation range (5-110 kΩ). In [16], a method based on the current compensation technique is proposed, which includes a current self-compensator and an improved current steering digital-to-analog converter (DAC). This approach offers lower power consumption, but the compensable range is limited to only 100 mV.…”
Section: Introductionmentioning
confidence: 99%