A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array

Read/write margin enhanced 10T SRAM for low voltage application

“…The failure rate is expressed as P Fail . For standby and read operation, the P Fail is determined by the SNM < V Thermal , where the V Thermal is the thermal voltage which is 26 mV at normal temperature, and for write operation, the P Fail is determined by the WM < 0 [ 1,6,7,9]. Due to retention stability is typically stronger compared to read data stability [6], this paper just concerns the read and write operation.…”

“…As can be seen, the read as well as write failure probability of the proposed 10T cell is orders of magnitude smaller compared that of conventional 6T cell. In addition, according to [1,6,7,9], the VDD min is defined as the minimum supply voltage at which the target yield can be achieved, and determined by maxfVDD hold min ; VDD read min ; VDD write min g, where the VDD hold min , VDD read min , and VDD write min are the minimum VDD in standby, read, and write operation, respectively. Additionally, due to VDD hold min is much lower than VDD read min and VDD write min [6], the Table IV gives the VDD min of different SRAM cells determined by VDD read min and VDD write min , assuming the P Failis is 10 À5 .…”

“…Although supply voltage scaling has been proved to be the most effective method for energy saving [1,2,3,4,5,6], it will seriously deteriorate the read stability and write ability of the memory cell. Moreover, due to the process variations existing, the performance described above will be further deteriorated in low voltage, also in the future process nodes, which will result in the failure probability of read or write operations increasing [2,6,7,8,9,10]. Thus, the trade-off between performance and power should be considered.…”

“…However, this strategy will weaken the write ability. Moreover, with the effect of process variations, the robustness of SRAM cell will be exacerbated, and the VDD min will be further limited [1,2,6,7,9].…”

“…To improve the write margin and read stability for conventional 6T SRAM, different types SRAM cell topologies as well as assist circuit has been proposed [1,2,3,6,7,8,9,10,11,12,13]. Decoupling the storage nodes with bit-line or lowering the voltage drop between the driver and access transistors is the efficient way to enhance read stability [11].…”