A Rapid Prototyping Environment for Wireless Communication Embedded Systems

Jones, Bryan A.; Cavallaro, Joseph R.

doi:10.1155/s111086570330304x

Cited by 3 publications

(3 citation statements)

References 19 publications

(13 reference statements)

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“…Second, the design was specified using several languages: an equation description language, a block diagram language, and code in the C language, running on the DSP in the prototype. In the Rice testbed environment, we integrate the two locations (host and DSP/FPGA prototype) and three languages (Simulink, Matlab, and "C") inherent in DSP design [4]. The Wrapper, a software tool developed by at Rice, enables the designer to easily incorporate equations or "C" programs into a block diagram.…”

Section: Rapid Prototyping Design and System Partitioning Toolsmentioning

confidence: 99%

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Cavallaro

2002

Wireless Personal Communications

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Abstract. Next-generation wireless computing platforms will contain flexible communications capabilites. At Rice University, the Rice Everywhere NEtwork (RENÉ) project is investigating a multi-standard, multi-tier integration of W-CDMA cellular systems, high speed wireless LANs, and home wireless networks. There are many challenges in mapping these advanced communication algorithms to real-time hardware computing platforms. In this paper, we present current work on the development of a reconfigurable baseband physical layer containing DSP processors and FPGA accelerators. Our goal is the design of a multi-tier network interface card (mNIC) which is capable of exploiting efficient, low-power reconfiguration.

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Section: Rapid Prototyping Design and System Partitioning Toolsmentioning

confidence: 99%

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Cavallaro

2002

Wireless Personal Communications

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“…On the other hand, FPGAbased implementations for parallel and successive interference cancellation receivers have been, respectively, developed in [19] and [41]. Rapid prototyping targeted on FPGAs is proposed in [26,27] and [28]. In [30] efficient VLSI architectures for multiuser channel estimation base on maximum likelihood technique are proposed.…”

Section: Introductionmentioning

confidence: 99%

Real-time DSP and FPGA Implementation of Wiener LMS Based Multipath Channel Estimation in 3G CDMA Systems

Ouameur

Massicotte

2007

J VLSI Sign Process Syst Sign Image Video Technol

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This paper investigates real-time DSP and FPGA implementations of a low complexity technique for asynchronous multiuser delay acquisition and time varying channel tracking for multipath channels in WCDMA and cdma2000 systems. A multiuser-LMS-like structure along with smoothing/prediction filters to improve tracking quality is reviewed. We investigate an efficient implementation based on FFT/IFFT technique, under fixed-point data representation and computation constraint. The measured BER reveals that fixed-point implementation is feasible at possibly no performance degradation. Based on real time execution made on a fixed-point high performance DSP, the maximum number of users is 15 and 17 for the proposed method and correlator, respectively. Due to the inherent parallelism and regular data flow FPGA implementation is suggested wherein a maximum number of users more than 80 can be afforded in Xilinx Virtexi II Pro device.

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“…Moreover, the real-time implementation aspect of MUDs is also well documented (e.g., [6][7][8][9]). The rapid prototyping targeted on field-programmable gate arrays (FPGAs) is also proposed [10][11][12]. These works demonstrate several limitations in practical systems in terms of timing and algorithm and hardware constraints (e.g., arithmetic complexity, memory access requirements, data flow) [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of an MUD Based on Cascade Filters for a WCDMA System

Massicotte

Dahmane

2006

EURASIP J. Adv. Signal Process.

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The VLSI architecture targeted on FPGAs of a multiuser detector based on a cascade of adaptive filters for asynchronous WCDMA systems is presented. The algorithm is briefly described. This paper focuses mainly on real-time implementation. Also, it focuses on a design methodology exploiting the modern technology of programmable logic and overcoming the limitations of commercial tools. The dedicated architecture based on a regular structure of processors and a special structure of memory exploiting FPGA architecture maximizes the processing rate. The proposed architecture was validated using synthesized data in UMTS communication scenarios. The performance goal is to maximize the number of users of different WCDMA data traffics. This dedicated architecture can be used as an intellectual property (IP) core processing an MUD function in the system-onprogrammable-chip (SOPC) of UMTS systems. The targeted FPGA components are Virtex-II and Virtex-II Pro families of Xilinx.

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A Rapid Prototyping Environment for Wireless Communication Embedded Systems

Cited by 3 publications

References 19 publications

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Untitled

Real-time DSP and FPGA Implementation of Wiener LMS Based Multipath Channel Estimation in 3G CDMA Systems

FPGA Implementation of an MUD Based on Cascade Filters for a WCDMA System

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