A Range-Extended and Area-Efficient Time-to-Digital Converter Utilizing Ring-Tapped Delay Line

Wang, Xingang; Wang, Fei; Jia, Rui; Chen, Rui; Tian, Zhigang; Yang, Haigang

doi:10.1587/transele.e96.c.1184

Cited by 2 publications

(3 citation statements)

References 30 publications

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“…Time-to-digital converters (TDCs) measure the time interval of two asynchronous timing signals [1]. Dual-slope [2,3] and triple-slope [4] methods are developed in analogue TDCs to quantize the time interval.…”

Section: Introductionmentioning

confidence: 99%

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Successive approximation time-to-digital converter based on vernier charging method

Wang

Yang

Wang

et al. 2014

IEICE Electron. Express

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A successive approximation time-to-digital converter (TDC) is presented. The proposed TDC is based on the vernier charging method, and characterized with its timing resolution independent of the period of the reference clock. Further by including voltage ratio together with both current and capacitor ratios to enlarge the pulse stretch factor, a higher timing resolution is attained. The circuit is implemented in a 130 nm CMOS process and occupies an area of 0.32×0.21 mm 2 . According to the simulation results, the proposed TDC achieves typically 6.25 ps resolution and consumes 0.9 mW from a 1.5 V supply voltage.

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Section: Introductionmentioning

confidence: 99%

“…Initially, the voltages of master charge pump (MCP) V m and slave charge pump (SCP) V s are precharged to the same V ref 1 . Then the capacitor C in MCP is charged with a constant current N ·I during T ff , while it is discharged with the same current during T fb .…”

Section: Introductionmentioning

confidence: 99%

Successive approximation time-to-digital converter based on vernier charging method

Wang

Yang

Wang

et al. 2014

IEICE Electron. Express

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“…Based on the method of built-in self-test (BIST), the on-chip jitter measurement circuits are used to solve the above problems during recent years [2,3,4].…”

Section: Introductionmentioning

confidence: 99%

On-chip long-term jitter measurement for PLL based on undersampling technique

Cai

Que

et al. 2013

IEICE Electron. Express

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An all-digital circuit for on-chip measuring the long-term jitter of Phase-Locked Loop (PLL) using the undersampling technique is presented in this paper. The circuit comprises the undersampling circuit, which samples the PLL output signal and the data analysis circuit, which calculates the statistical value of the jitter. The data statistics approach is based on accumulating data from multiple edge regions with cycle edge alignment, which is suitable for measuring the long-term jitter of PLL clock signal. The proposed built-in self-test (BIST) circuit can test the PLL output signal whose frequency is greater than 1 GHz. And it can provide high measurement resolution that is up to 1 ps. The circuit was designed in Verilog, and fabricated in TSMC 130 nm CMOS process. Simulated results show the possibility of detecting 45 ps RMS long-term jitter of a 1 GHz clock with less than 2% error.

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A Range-Extended and Area-Efficient Time-to-Digital Converter Utilizing Ring-Tapped Delay Line

Cited by 2 publications

References 30 publications

Successive approximation time-to-digital converter based on vernier charging method

Successive approximation time-to-digital converter based on vernier charging method

On-chip long-term jitter measurement for PLL based on undersampling technique

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