A RAM based CMOS histogrammer integrated circuit

Abstract

A Histogramming integrated circuit h a s been designed with 256 24 bit cells , the pipelined R A M based architecture h a s been designed t o give histogram capture rates of at least 8 M h z . T h e chip i s capable of histogramming a n entire 512 x 512 image with a n eight bit grey level in real t i m e ', and i s fully cascadable f o r both increased histogram resolution or capacity. . T h e R A M i s accessable f o r r a n d o m read/write operations through the 24 bit data and 8 bit address busses. A dditional features include global thresholding ,sequential read/clear and a simple self test o n the R A M . T h e chip w a s designed using a n integrated design s y s t e m with a ramcell compiler and is being fabricated o n a 2 m i c r o n CMOS technology.