A quick safari through the reconfiguration jungle

Schaumont, Patrick; Verbauwhede, Ingrid; Keutzer, Kurt; Sarrafzadeh, Majid

doi:10.1145/378239.378404

Cited by 75 publications

(32 citation statements)

References 12 publications

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“…Increasingly we are seeing reconfigurable devices emerge as the flexible and highperformance workhorses inside a variety of high performance embedded computing systems [4,6,8,15,20,29]. The power of reconfigurable systems lies in the immense amount of flexibility that is provided.…”

Section: Reconfigurable Systemsmentioning

confidence: 99%

Policy-Driven Memory Protection for Reconfigurable Hardware

Huffmire

Prasad

Sherwood

et al. 2006

Computer Security – ESORICS 2006

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Abstract. While processor based systems often enforce memory protection to prevent the unintended sharing of data between processes, current systems built around reconfigurable hardware typically offer no such protection. Several reconfigurable cores are often integrated onto a single chip where they share external resources such as memory. While this enables small form factor and low cost designs, it opens up the opportunity for modules to intercept or even interfere with the operation of one another. We investigate the design and synthesis of a memory protection mechanism capable of enforcing policies expressed as a formal language. Our approach includes a specialized compiler that translates a policy of legal sharing to reconfigurable logic blocks which can be directly transferred to an FPGA. The efficiency of our access language design flow is evaluated in terms of area and cycle time across a variety of security scenarios.

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Section: Reconfigurable Systemsmentioning

confidence: 99%

Policy-Driven Memory Protection for Reconfigurable Hardware

Huffmire

Prasad

Sherwood

et al. 2006

Computer Security – ESORICS 2006

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“…Computer architects have been studying the dynamically reconfigurable computer [1] for a number of years. New capabilities such as on-demand computing power, self-adaptiveness and self-optimization capabilities by restructuring the hardware on the fly at run-time is seen as a driving technology factor for current research initiatives such as autonomic [2,3] and organic computing [4,5].…”

mentioning

confidence: 99%

The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer

Majer

Teich

Ahmadinia³

et al. 2007

J VLSI Sign Process Syst Sign Image Video Technol

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Abstract. Computer architects have been studying the dynamically reconfigurable computer [1] for a number of years. New capabilities such as on-demand computing power, self-adaptiveness and self-optimization capabilities by restructuring the hardware on the fly at run-time is seen as a driving technology factor for current research initiatives such as autonomic [2,3] and organic computing [4,5]. Much research work is currently devoted to models for partial hardware module relocation [6] and dynamically reconfigurable hardware reconfiguration on e.g., FPGAbased platforms. However, there are many physical restrictions and technical problems limiting the scope or applicability of these approaches. This led us to the development of a new FPGA-based reconfigurable computer called the Erlangen Slot Machine. The architecture overcomes many architectural constraints of existing platforms and allows a user to partially reconfigure hardware modules arranged in so-called slots. The uniqueness of this computer stems from a) a new slot-oriented hardware architecture, b) a set of novel inter-module communication paradigms, and c) concepts for dynamic and partial reconfiguration management.

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“…A taxonomy of reconfigurable logic devices is given in [2]. In order to handle the routing area overhead of FPGAs and herewith configurations' size another approach are coarse-grained reconfigurable architectures.…”

Section: Related Workmentioning

confidence: 99%

Regular mapping for coarse-grained reconfigurable architectures

Hannig

Dutta

Teich

2004 IEEE International Conference on Acoustics, Speech, and Signal Processing

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Similar to programmable devices such as processors or micro controllers also reconfigurable logic devices can be built as software, by programming the configuration of the device. In this paper, we present an overview of constraints which have to be considered when mapping applications to coarse-grained reconfigurable architectures. The application areas of most of these architectures addressing computational-intensive algorithms like video and audio processing or wireless communication. Therefore, reconfigurable arrays are in direct competition with DSP processors which are traditionally used for digital signal processing. Hence, existing mapping methodologies are closely related to approaches from the DSP world. They try to employ pipelining and temporal partitioning but they do not exploit the full parallelism of a given algorithm and the computational potential of typically 2-dimensional arrays. We present a first case study for mapping regular algorithms onto reconfigurable arrays by using our design methodology which is characterized by loop parallelization in the polytope model. The case study shows that our regular mapping methodology may lead to highly efficient implementations taking the constraints of the architecture into account.

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A quick safari through the reconfiguration jungle

Cited by 75 publications

References 12 publications

Policy-Driven Memory Protection for Reconfigurable Hardware

Policy-Driven Memory Protection for Reconfigurable Hardware

The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer

Regular mapping for coarse-grained reconfigurable architectures

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