A qualification platform for design reuse

Seepold, Ralf; Madrid, Natividad Martínez; Vörg, Andreas; Radetzki, Marian; Neumann, Paul G.; Haase, Joachim

doi:10.1109/isqed.2002.996698

Cited by 12 publications

(7 citation statements)

References 4 publications

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“…It is hard to use spreadsheets in EDA-based design flow and is also hard to automate the measurement process. An automatic qualification methodology based on EDA flow is presented in [5] [6]. The common grounds in these papers: (1) Using commercial EDA tools as qualification tools.…”

Section: Related Workmentioning

confidence: 99%

A practical IP quality measurement framework

Zhou

Gao

Chan

2007

2007 7th International Conference on ASIC

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Objective and quantifiable measurement is critical to the successful development of today's complex ASIC design. In this paper, we propose a practical digital IP core quality measurement framework which is based on objective quality metrics. This measurement framework can be implemented as a quality measurement program within ASIC design flow. This framework will help IP designers to reach a consensus on which quality attributes are important for a given IP block. As a case study, the presented quality measure framework has been implemented in a wireless communication chip project.

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Section: Related Workmentioning

confidence: 99%

A practical IP quality measurement framework

Zhou

Gao

Chan

2007

2007 7th International Conference on ASIC

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“…Therefore, as in [7], we divide the IPQ rules into two categories ⎯ "predefined" and "user-defined". The predefined rules are the ones that are loaded in the beginning and cannot be added, removed or modified during the execution.…”

Section: Creation Of Ip Qualification Rulesmentioning

confidence: 99%

“…In [6], the authors implemented an automatic qualification framework with several qualification methods, like completeness check, coding guidelines and design rule checks, verification and synthesis qualification, etc. The work in [7] also developed a methodology for automated and design flow-oriented IP quality checks and the authors in [8] proposed an automatic qualification flow for technology independent soft IP.…”

Section: Introductionmentioning

confidence: 99%

QuteIP: An IP qualification framework for System on Chip

Hung

Lin

Huang

2007

2007 IEEE International SOC Conference

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The robustness and reusability of Intelligent Properties (IPs) are the keys to the success of the modern System on Chip (SoC) designs. Therefore, it is very important to implement a rigid IP qualification (IPQ) framework to ensure the quality of IPs in the SoC design flow. In this paper, we carefully examine the advancements and limitations of previous IPQ tools and propose several novel concepts and methodologies to construct a new IPQ framework. We make the framework easily configurable so that it can be applied to different IP vendors with different IP users' needs. We design the user interface from the practicality point of view so that it is simple, yet complete enough to support various usages in the IP qualification process. Most important of all, our implementation does not include any proprietary information so that the readers should be able to reconstruct a similar IPQ framework on their own. We have deployed our framework to several IP design teams and their feedbacks showed that our IPQ framework can help them reduce the time in design and greatly improve the quality of their IPs.

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“…On the other hand, formal verification of such systems suffers from state explosion. However, it can often be assumed that the design of each individual component has been verified [33] and can be considered to be correct. What is still needed to be verified is the glue logic and the interaction between components over the glue logics.…”

Section: Introductionmentioning

confidence: 99%

Formal verification of component-based designs

Karlsson

Eles

Peng

2007

Des Autom Embed Syst

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Embedded systems are becoming increasingly common in our everyday lives. As technology progresses, these systems become more and more complex, and designers handle this increasing complexity by reusing existing components (Intellectual Property blocks). At the same time, the systems must fulfill strict requirements on reliability and correctness.This paper proposes a formal verification methodology which smoothly integrates with component-based system-level design using a divide and conquer approach. The methodology assumes that the system consists of several reusable components, each of them already formally verified by their designers. The components are considered correct given that the environment satisfies certain properties imposed by the component. The methodology verifies the correctness of the glue logic inserted between the components and the interaction of the components through the glue logic. Each such glue logic is verified one at a time using model checking techniques.Experimental results have shown the efficiency of the proposed methodology and demonstrated that it is feasible to apply such a verification methodology on real-life examples.

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A qualification platform for design reuse

Cited by 12 publications

References 4 publications

A practical IP quality measurement framework

A practical IP quality measurement framework

QuteIP: An IP qualification framework for System on Chip

Formal verification of component-based designs

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