A Quadrature Single Side-Band Mixer with Passive Negative Resistance in Software-Defined Frequency Synthesizer

Abstract

Software-defined radio (SDR) is a good solution for complying with the existing and incoming protocols for emerging wireless sensor networks (WSN) and internet of things (IoT) applications. The frequency synthesizer in a SDR tranceiver usually consists of a phase locked loop (PLL) and a post synthesizer. The PLL is the narrow band signal source and the post synthesizer generates wideband outputs by mixing and dividing. Compared with a frequency synthesizer utilizing the wideband PLL, this synthesizer features relatively constant loop parameters and mitigates the requirement for the oscillator. In this paper, a quadrature single side-band (QSSB) mixer with the proposed passive negative resistance (PNR) for frequency mixing in a post synthesizer is presented. The PNR is achieved by biasing the Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET) of the cross-coupled pair at the deep-triode region periodically and incorporates an inductor and a cap-array as the mixer load. Compared with the traditional single side-band mixers utilizing Inductor-Capacitor (LC) resonant loads or quality factor enhanced (Q-enhanced) LC resonant loads, which suffer from a selectivity versus working range trade-off, the mixer employing the proposed loading structure provides not only a wide operating range, but also a superior image side-band rejection ratio (ISRR). Moreover, the oscillating risk in conventional mixers adopting Q-enhanced LC resonant loads is eliminated. A wideband frequency synthesizer employing the proposed mixer was implemented in a TSMC 0.18 µm CMOS process and the mixer performed ISRR of 40–57 dB and 30–57 dB across 2.5–3 GHz and 2.3–3.2 GHz, respectively. The power consumption of the QSSB mixer, including buffer, is 18 mA from a 1.8 V supply and the active area is 0.445 mm2. The measurement results provide validation that the proposed QSSB mixer is suitable for wideband software-defined frequency synthesizers and other frequency generating systems.

Design of Digital Frequency Synthesizer for 5G SDR Systems

“…In [19] developed transient PLL with switched capacitors to cover a frequency range of several GHz (>10GHz) for implementing SDR in avionic communication applications. The single mixer based PLL core reduces the settling time into 3.92 μs with suppressed total phase noise.…”

Current/Voltage Controlled Quadrature Sinusoidal Oscillators for Phase Sensitive Detection Using Commercially Available IC

“…The equivalent circuit of LT1228 is drawn as shown in Figure 3c. The ideal terminal characteristic of LT1228 is shown in (9): From (9), the ZT represents the trans-resistance gain of the current feedback amplifier. Ideally, the RT approaches infinity.…”

“…This sort of oscillator is called a voltage controlled oscillator (VCO) or current controlled oscillator (CCO). Many voltage controlled oscillators are found in sensor applications, for example, in impedance spectroscopy [1], microelectromechanical systems (MEMS) sensor [4], IoT sensors [5,6], motion detection sensors [7], sensor readout circuit [8], wireless sensor network [9][10][11], basal-body-temperature detection sensor [12], image sensor [13], intelligent human sensing system [14], etc. These voltage controlled oscillators are designed and implemented in CMOS chips, which provides many advantages, for example, low power consumption, compact size, low voltage operation, high speed, etc.…”

A novel voltage-mode universal second-order filter using five single ended OTAs and its quadrature sinusoidal oscillator application

“…[17][18][19][20][21][22] It can be seen that the proposed universal VM SEOTA-based second-order filter can simultaneously achieve all the above imported properties. In addition, filters and oscillators are used in measurement and control system, such as in phase sensitive detection system, 23 wireless sensor network, 24 and the high fidelity 3-way speaker. 25 Compared with the five SEOTAs and two ground capacitors circuits proposed in Wang et al, [19][20][21] the proposed circuit can realize universal VM second-order NLPF, NHPF, IBPF, NBRF, and NAPF voltage responses by appropriately connecting triple-input voltage signals, which can reduce the noise interference generated at the input voltage terminal and circuit complexity.…”