A pyramid vector quantizer chip for HDTV applications

Abstract

Abstract. The quantization process in bit-rate reduction for video coding has been taken into account. Because, at least in theory, vector quantization obtains better performance than scalar quantization, a pyramid vector quantizer has been analysed. Some figures of performance have been estimated by Monte Carlo simulation and, after analysing the problem of vector formation. directly on a typical video coding scheme. In the past, a single-chip dedicated processor for implementation of the PVQ was presented with the conclusion that the allowed quantization sample rate was no greater than 16 kHz. In this work ASIC-oriented modifications of the base algorithm are described and an ASIC design for the PVQ is presented. The architecture of the integrated circuit was obtained by means of the systolic macrocell approach. A system throughput greater than 70 MSa/s was allowed that extends the range of application of the PVQ up to HDTV digital video coding.