A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector

Choi, Jae Hyun; Yoo, Seyeon; Lim, Younghyun

doi:10.1109/jssc.2016.2574804

Cited by 70 publications

(10 citation statements)

References 24 publications

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“…Results in Figure 12 show an expected degradation of EVM values with increasing values of jitter for all the cases. Although not directly compared in Figure 12, the performance of table-based PWM with the presence of jitter values around 0.2ps like those reported in previous studies [39][40][41] is better than baseband PWM and similar to RF PWM for the same T res even without considering this effects, which can be observed in Figure 10. Taking as an example the EVM value for table-based PWM with jitter values of 0.2ps is −32.3dB for T res = 3.33ps; for the same time resolution, RF PWM and baseband PWM present EVM values of −32.2 and −29.1dB, respectively.…”

Section: Resultssupporting

confidence: 58%

Table‐based PWM for all‐digital RF transmitters

Morales

Chierchie

Mandolesi

et al. 2018

Circuit Theory & Apps

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Summary In this paper, a novel pulse‐width modulator (PWM) for an all‐digital PWM transmitter based on switching amplification is presented. In this approach, each symbol is represented by a sequence of pre‐computed PWM pulse widths stored in a table that results in reduced error vector magnitude (EVM). A high‐resolution pulse former is then used to build the bipolar radio frequency (RF) signal. Simulations and comparisons to other approaches reported in the literature under different oversampling ratios and finite time resolutions are presented. The impact of nonlinearities in the variable duty‐cycle generator is also analyzed to demonstrate the robustness of the proposed technique.

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Section: Resultssupporting

confidence: 58%

Table‐based PWM for all‐digital RF transmitters

Morales

Chierchie

Mandolesi

et al. 2018

Circuit Theory & Apps

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“…Injection locking has been proven to be a promising technique to achieve low jitter performance in a PLL [31][32][33][34][35]. Therefore, it is adopted to reduce the phase noise by eliminating the DCO jitter accumulation at every reference cycle.…”

Section: Injection Lockingmentioning

confidence: 99%

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits

Yang

Zhao

et al. 2019

Sci. China Inf. Sci.

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This paper proposes a synthesized injection-locked bang-bang phased-locked loop (SILBBPLL) with high digital controlled oscillator (DCO) frequency resolution. The SILBBPLL is expressed with hardware description language and automatically placed & routed (APR) by using standard digital circuit design flow. As the mismatch issues of the circuits are not considered carefully during the APR design flow, the phase noise performance is severely deteriorated. We adopt pulse injection locking technique to improve the phase noise performance. The DCO frequency resolution is critical for reducing the reference spur in a digital injection-locked PLL. Therefore, we propose novel frequency tuning circuits to increase the DCO frequency resolution so that the reference spurs are reduced. The frequency tuning circuits consist of a standard cell based high-linearity output feedback DAC (OFDAC) and two custom varactors. The OFDAC is used to tune the frequency of the DCO with the custom varactor precisely. The custom varactor is firstly designed, added into the standard cell library, and APR with the standard cells. The SILBBPLL chip with a core area of 0.008 mm 2 is implemented in 65 nm CMOS process. When operating at 1.8 GHz, the measured results show that the root-mean-square (RMS) jitter integrated from 10 kHz to 100 MHz is 1.1 ps, and the power consumption is 1.5 mW with a 0.8-V supply. The proposed SILBBPLL achieves a figure-of-merit (FoM) of −237.4 dB and a reference spur of −50.9 dBc. Keywords synthesized all-digital phased-locked loops (ADPLL), bang-bang phased-locked loop (BBPLL), automatically placed & routed (APR), output feedback DAC (OFDAC), injection-locked Citation Yang J C, Zhang Z, Qi N, et al. A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits.

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“…This is because the structure has a PLL loop path and an injection path. A timing problem arises because the two paths operate independently [ 13 ]. To overcome this timing issue, an ILFM with two separate loops has been proposed.…”

Section: Prior Ilfm Structuresmentioning

confidence: 99%

“…Recently, several papers have been published that suggest some approaches to overcome this problem [ 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 ]. In References [ 10 , 11 , 12 , 13 ], the structure using the most basic single-loop PLL or DLL is used. However, this structure cannot prevent the real-time frequency drift that occurs through supply voltage and temperature variations.…”

Section: Introductionmentioning

confidence: 99%

A Design of Small Area, 0.95 mW, 612–1152 MHz Open Loop Injection-Locked Frequency Multiplier for IoT Sensor Applications

Kim

et al. 2018

Sensors

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This paper presents a 612–1152 MHz Injection-Locked Frequency Multiplier (ILFM). The proposed ILFM is used to send an input signal to a receiver in only the I/Q mismatch calibration mode. Adopting a Phase-Locked Loop (PLL) to calibrate the receiver places a burden on this system because of the additional area and power consumption that is required. Instead of the PLL, to satisfy high-frequency, low-jitter and low-area requirements, a Ring Oscillator is adopted in the system. The free-running frequency of the ILFM is automatically and digitally calibrated to reflect the frequency of the injected signal from the harmonics of the reference clock. To control the frequency of the ILFM, the load current is digitally tuned with a 6-bit digital control signal. The proposed ILFM locks to the target frequency using a digitally controlled Frequency Locked Loop (FLL). This chip is fabricated using 1-poly 6-metal 0.18 µm CMOS and has achieved the wide tuning range of 612–1152 MHz. The power consumption is 0.95 mW from a supply voltage of 1.8 V. The measured phase noise of the ILFM is −108 dBc/Hz at a 1 MHz offset.

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A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector

Cited by 70 publications

References 24 publications

Table‐based PWM for all‐digital RF transmitters

Table‐based PWM for all‐digital RF transmitters

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits

A Design of Small Area, 0.95 mW, 612–1152 MHz Open Loop Injection-Locked Frequency Multiplier for IoT Sensor Applications

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