A prototype architecture for the accurate modeling of Rayleigh fading waveforms

Surendra, B.; Srinivas, B.; Rambabu, C.; Gogoi, Anup Kumar

doi:10.1109/icics.2003.1292630

Cited by 6 publications

(3 citation statements)

References 7 publications

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“…Using FDATool we can easily convert the filter structures as per required. Filter coefficient for the above designed filter is stored in the LUTs [8] which are then processed.…”

Section: B Hdl Design Of Channel Estimation Modelmentioning

confidence: 99%

Adept spectral filter for fading nonisotropic channel model

Francis

Cheriyan

2014

2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)

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In this paper a novel efficient spectrum shaping filter for fading nonisotropic channel model is being proposed. Wireless communication system's evaluation is hampe red due to time consuming, complex and inaccurate testing phase. The evaluation can be made proficient and dependable by creating channel environment for testing phase based on filter approach. During transmission of information through free space signal has to overcome fading and scattering effects. Channel environs has to be created by considering statistical properties and power spectra to replicate the nature of fading and scattering. Envelope shaping and spectrum filter can be realized for estimating channel effects. Envelope shaping filter can be modelled as IIR filter and spectrum filter as a multirate filter. In this paper a spectrum filter based on HDL is being proposed and AS IC results for 130nm standard library is considered.

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“…Using FDATool we can easily convert the filter structures as per required. Filter coefficient for the above designed filter is stored in the LUTs [8] which are then processed.…”

Section: B Hdl Design Of Channel Estimation Modelmentioning

confidence: 99%

Adept spectral filter for fading nonisotropic channel model

Francis

Cheriyan

2014

2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)

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“…reported slice usage in [19] is 6178 on Virtex-xc2vI500-5 platform. Similarly the LUTs utilized in our design are 473 and 574 in Spartan and Virtex4 platforms respectively, while the reported LUT usage in [19] is 6232 on Virtex-xc2vI500-5 platform.…”

Section: A Resource Consumptionmentioning

confidence: 99%

Hardware realization of a low-complexity fading filter for multipath Rayleigh fading simulator

2010

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Abstract-A low-complexity high performance Rayleigh fading simulator, and its Field Programmable Gate Array (FPGA) implementation are presented. This proposed method is a variant of the method of filtering of the white Gaussian noise where the filter design is accomplished in the analog domain and transferred into digital domain. The proposed model is compared with improved Jakes' model [1], auto-regressive filtering [2] and IDFT [3] techniques, in performance and computational complexity. Proposed method outperforms AR(20) filter and modified Jakes' generators in performance. Although IDFT method achieves the best performance, it brings a significant cost in storage and is undesirable. The proposed method achieves high performance with the lowest complexity, and its performance has been verified on Virtex4 and Spartan3e FPGA platforms. Our fixed-point Rayleigh fading-channel simulator utilizes only 2% of the configurable slices, lOA. of the Look-Up- Table (LUT) resources and 3°A. of the dedicated multipliers on a Xilinx Virtex4 -xc4vsx35 FPGA platform.

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“…Different hardware designs have been reported in the literature [9]- [16]. Despite its inaccuracies, (see [5], [6]) the sum-of-sinusoids method has been widely used due to its simplicity and efficient implementation [10]- [13], [16]. Because of its sensitivity to quantization errors, using the filter-based technique can be challenging.…”

Section: Motivation and Backgroundmentioning

confidence: 99%

A Single FPGA Filter-Based Multipath Fading Emulator

Fard

Alimohammad

Cockburn

et al. 2009

GLOBECOM 2009 - 2009 IEEE Global Telecommunications Conference

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Emulation of fading channels is a key step in the design and verification of wireless communication systems. Testing wireless transceivers with actual fading channels is inconvenient due to unrepeatable and uncontrollable channel conditions. In this paper we present a compact field-programmable gate array (FPGA) implementation for a circuit that generates temporallycorrelated fading variates for emulating multipath fading radio channels. The implemented fading emulator is flexible enough to model different propagation scenarios accurately and is compact enough that it can be implemented on the same FPGA with the design under test (DUT) for greater emulation efficiency and speed-up. Several streams of Rayleigh or Rician fading variates are generated by passing independent samples of Gaussian noise through spectrum shaping filters. The new baseband emulator is fully parameterizable and can emulate a wide variety of single and multiple antenna scenarios.This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the IEEE "GLOBECOM" 2009 proceedings.

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A prototype architecture for the accurate modeling of Rayleigh fading waveforms

Cited by 6 publications

References 7 publications

Adept spectral filter for fading nonisotropic channel model

Adept spectral filter for fading nonisotropic channel model

Hardware realization of a low-complexity fading filter for multipath Rayleigh fading simulator

A Single FPGA Filter-Based Multipath Fading Emulator

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