A prolog implementation of an instruction‐level processor simulator

Abstract

This paper describes the implementation of a Prolog‐based, instruction‐level simulator used in the design of a new processor. The adaptability of Prolog as a hardware description language is reported. Prolog was a good choice for purposes of rapid prototyping and as a means to derive high‐level executable specifications for the instruction set. The rapid software development strategy entailed a price to be paid in the form of a relatively slow performance. Methods to improve the speed of Prolog‐based simulators are suggested.

The role of the computer architecture simulator in the laboratory

“…In a previous work, an instructionlevel processor simulator in Prolog [28 ] has been described . That paper, however , given its indicative nature, is to b e considered an introduction to the use o f Prolog in this field .…”