A Programmable, Scalable Platform for Next-Generation Networking

Georgiou, C.J.; Salapura, Valentina; Denneau, Monty

doi:10.1016/b978-012198157-0/50004-0

Cited by 2 publications

(4 citation statements)

References 4 publications

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“…Our implementation of the Fibre Channel protocol showed that less than 4 Kbytes of I-cache per processor were sufficient to get instruction hit rates of more than 98%, because of the small footprint of the code [1]. Four cores share a local SRAM, for storing their stack and local variables, and parts of packets that need to be processed, such as header fields.…”

Section: Figure 3: Soc Employing Self-contained Processor Based Macromentioning

confidence: 98%

“…The processors have a reduced general purpose instruction set derived from the PowerPC architecture, and a single-issue architecture with a four-stage deep pipeline. Each processor has its own register file, ALU, and instruction sequencer [1]. The size of the instruction cache is 32 Kbytes, which is sufficient for network applications, as shown in [11].…”

Section: Figure 3: Soc Employing Self-contained Processor Based Macromentioning

confidence: 99%

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An efficient system-on-a-chip design methodology for networking applications

Salapura

Georgiou

Nair

2004

Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

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This has led to the offloading of many of the networking and protocol processing functions from host processors into host-busadapters (HDAs) or network interface controllers (NICs). Initially, most HDAs and NICs were implemented in ASICs using hardwired logic. But as the need to implement complex network protocols arose, such as iSCSI, programmable solutions have become attractive because of a number of advantages they offer: they can accommodate different and evolving protocols; they are easily upgradeable via program changes; they offer a faster time to market. An example of such a programmable solution that is implemented in the form of a scalable, multiprocessor architecture and combines multiple processor cores and hardware accelerators on a single chip can be found in a earlier paper [1]. This paper presents a System-on-a-Chip design methodology that uses a microprocessor subsystem as a building block for the development of chips for networking applications. The microprocessor subsystem is a self-contained macro that functions as an accelerator for computation-intensive pieces of the application code, and complements the standard components of the SoC. It consists of processor cores, memory banks, and well-defined interfaces that are interconnected via a high-performance switch. The number of processors and memory banks are parameters that can vary depending on the application to be implemented on the chip. Applications such as protocol conversion, TCP/IP off-load engine, or firewalls can be implemented with processor counts ranging from 8 to 128.Another trend that has emerged in the design of high-speed networking components is the system-on-chip (SoC) approach [2]. SoC designs have provided integrated solutions for communication, multimedia, and consumer electronics applications. To meet performance and functionality requirements, current SoC designs typically include a general-purpose processor, one or more DSPs (Digital Signal Processors), multiple fixed function silicon accelerators, and embedded memory. For example, a CDMA cell phone might have 800,000 to 3 million gates dedicated to hardware accelerators, and up to four DSPs performing the remainder of the processing.

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Section: Figure 3: Soc Employing Self-contained Processor Based Macromentioning

confidence: 98%

Section: Figure 3: Soc Employing Self-contained Processor Based Macromentioning

confidence: 99%

An efficient system-on-a-chip design methodology for networking applications

Salapura

Georgiou

Nair

2004

Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Self Cite

View full text Add to dashboard Cite

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“…SOC systems are becoming widely used and more important not only for general purpose microprocessor chips, but also in computation-intensive embedded applications such as communication data stream devices and video-communicative mobile equipment [3]. Highly integrated network chips also serve as building blocks for constructing mobile computers based on network architecture [4].…”

Section: Introductionmentioning

confidence: 99%

“…Highly integrated network chips also serve as building blocks for constructing mobile computers based on network architecture [4]. These highly integrated chips are used as design components for network applications [4,5].…”

Section: Introductionmentioning

confidence: 99%

A Time Division Multiplexing (TDM) Logic Mapping Method for Computational Applications

Jeong

Jinsuk

John

et al.

Lecture Notes in Computer Science

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This paper discusses a large number of logic circuit mapping methods for complex systems, focusing on network hardware system designs. This logic mapping technique enables significant logic simulation time savings by mapping identical logic processor modules. Under the logic mapping method which is called the time division multiplexing (TDM) logic mapping method, the speed of the required to simulate it is significantly reduced, compared with conventional mapping methods, when folding the identical modules into a single module copy is done at the hardware description language (HDL) level. In principle, this method can be applied to any type of a network design platform, e.g., communication data stream through physical channel (fiber optic line), video signal transfer logic display environment, etc. In this paper, we demonstrate this method using several configurations of the IBM Serial Link architecture.

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A Programmable, Scalable Platform for Next-Generation Networking

Cited by 2 publications

References 4 publications

An efficient system-on-a-chip design methodology for networking applications

An efficient system-on-a-chip design methodology for networking applications

A Time Division Multiplexing (TDM) Logic Mapping Method for Computational Applications

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