A programmable RFSoC in 16nm FinFET technology for wideband communications

Farley, Brendan; Erdmann, Christophe; Vaz, B.; McGrath, John; Cullen, Edward; Verbruggen, Bob; Pelliconi, Roberto; Breathnach, Daire; Lim, Peng; Boumaalif, Ali; Lynch, Patrick; Mesadri, Conrado; Melinn, David; Yap, Kwee Peng; Madden, Lachlan

doi:10.1109/asscc.2017.8240201

Cited by 19 publications

(28 citation statements)

References 2 publications

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“…If the RF DAC is integrated into digital ASIC (on the same die), it will be possible to save power and area by eliminating the serial link transceivers. The RF DAC can potentially fit in the same area as of the high-speed serial data link sender in digital ASIC, which implies no additional area is needed for monolithic integration of the RF DAC in digital ASIC [5].…”

Section: Digital Transmittermentioning

confidence: 99%

“…The frequency response of the RF DAC will have high energy lobe at f s or a multiple of f s depending on the oscillating pulse duration. The higher Nyquist images of the digital data at f s (or a multiple of f s ), will be the RF output signal of the RF DAC [5,7,12,19].…”

Section: Rf-sampling Dacsmentioning

confidence: 99%

“…The digital data is processed in the digital blocks and the sample rate is increased to the update rate of the RF DAC. In general two approaches exist for implementing a mixing RF DAC depending on how the mixing operation in each cell of the DAC is performed, as discussed in [19]: at the data path as ''mixing logic'' or modulating the tail current as ''series mixing'' and therefore various oscillating PAM signals have been used for RF DAC implementation such as continues sinusoidal [7,12], discrete oscillating PAM [20], or a bipolar rectangular [5,19]. To implement the RF DAC in a process that is compatible with co-integration by digital ASIC, mixing logic approach is preferred due to the voltage headroom limitations and also the ''digital-in-nature'' characteristic of this method, so that the RF DAC actually benefits from process scaling.…”

Section: Proposed Rf Dac-based Digital Transmittermentioning

confidence: 99%

“…This makes the DAC output impedance input codedependent, and causes non-linearity [10,16]. There are some techniques to overcome this limitation to some extent, for instance, by using bleeding current sources [5,10], still the achievable linearity for sub-10 GHz operation is very limited.…”

Section: Rf Dac Output Stage In Voltage-modementioning

confidence: 99%

“…In 12 bit RF DAC, there are 4095 unit elements and each R u has an area of 2.74 lm 2 , in total becomes 0.00112 mm 2 . Although this is only the area needed for resistors and not the complete design, it gives a good approximation of the required area and indicates that the proposed RF DAC area is very competitive, when compared to the state of the art RF DACs [5,13,14]. The NMOS and PMOS switches in each unit element are minimum sized (W = 300 nm, L = 20 nm) with m-factor of five (transistors M 1À4 in Fig.…”

Section: Transfer Functionmentioning

confidence: 99%

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A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters

Sadeghifar

Bengtsson

Wikner

2019

Analog Integr Circ Sig Process

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As the number of antenna elements increases in massive multiple-input multiple-output-based radios such as fifth generation mobile technology (5G), designing true multi-band base-station transmitter, with efficient physical size, power consumption and cost in emerging cellular frequency bands up to 10 GHz, is becoming a challenge. This demands a hard integration of radio components, particularly the radio's digital application-specific integrated circuits (ASIC) with high performance multi-band data converters. In this work, a novel radio frequency digital-to-analog converter (RF DAC) solution is presented, that is also capable of monolithic integration into today's digital ASIC due to its digital-in-nature architecture. A voltage-mode conversion method is used as output stage, and configurable mixing logic is employed in the data path to create a higher frequency lobe and utilize the output signal in the first or the second Nyquist zone. This 12-bit RF DAC is designed in a 22 nm FDSOI CMOS process, and shows excellent linearity performance for output frequencies up to 10 GHz, with no calibration and no trimming techniques. The achieved linearity performance is able to fulfill the high requirements of 5G base-station transmitters. Extensive Monte-Carlo analysis is performed to demonstrate the performance reliability over mismatch and process variation in the chosen technology.

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Section: Digital Transmittermentioning

confidence: 99%

Section: Rf-sampling Dacsmentioning

confidence: 99%

Section: Proposed Rf Dac-based Digital Transmittermentioning

confidence: 99%

Section: Rf Dac Output Stage In Voltage-modementioning

confidence: 99%

Section: Transfer Functionmentioning

confidence: 99%

See 3 more Smart Citations

A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters

Sadeghifar

Bengtsson

Wikner

2019

Analog Integr Circ Sig Process

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High-Speed ADCs for Wireless Base Stations

Verbruggen

Vaz

Erdmann

et al. 2019

Next-Generation ADCs, High-Performance Power Management, and Technology Considerations for Advanced Integrated Circuits

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Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC

et al. 2019

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A direct digital-to-RF converter (DRFC) is presented in this work. Due to its digital-in-nature design, the DRFC benefits from technology scaling and can be monolithically integrated into advance digital VLSI systems. A fourthorder single-bit quantizer bandpass digital Σ∆ modulator is used preceding the DRFC, resulting in a high in-band signal-to-noise ratio (SNR). The out-ofband spectrally-shaped quantization noise is attenuated by an embedded semidigital FIR filter (SDFIR). The RF output frequencies are synthesized by a novel configurable voltage-mode RF DAC solution with a high linearity performance.The configurable RF DAC is directly synthesizing RF signals up to 10 GHz in first or second Nyquist zone. The proposed DRFC is designed in 22 nm FDSOI CMOS process and with the aid of Monte-Carlo simulation, shows 78.6 dBc and 63.2 dBc worse case third intermodulation distortion (IM3) under process mismatch in 2.5 GHz and 7.5 GHz output frequency respectively.

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A programmable RFSoC in 16nm FinFET technology for wideband communications

Cited by 19 publications

References 2 publications

A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters

A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters

High-Speed ADCs for Wireless Base Stations

Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC

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