A programmable audio/video processor for H.320, H.324, and MPEG

Brinthaupt, D.; Knobloch, Jens; Othmer, J.; Petryna, B.; Uyttendaele, Matt

doi:10.1109/isscc.1996.488589

Cited by 16 publications

(1 citation statement)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The coding/encoding process of the H.263 standard may be implemented with the use of any of those multimedia enhanced DSPs (Brinthaupt, 1996) (Golston, 1996(Golston, )(0kamoto, 1996, which have been developed specifically for H.261 or MPEG 1. However, in terms of the mobile and portable use, there still remains much room for reducing both the power consumption and chip area of the codec core.…”

Section: Introductionmentioning

confidence: 99%

A Low-Power H.263 Video CoDec Core Dedicated to Mobile Computing

Miki

Fujita

Kobayashi

et al. 1997

VLSI: Integrated Systems on Silicon

View full text Add to dashboard Cite

A number of novel VLSI architectures are devised for an H.263 video codec core in terms of low bitrate visual communication. The potential of the practicability for mobile computing has been extremely explored by attempting not only to minimize the total chip area but also to reduce the power consumption to such an extent that the operation frequency can be slowed down to 15MHz. The whole encoding and decoding facilities have been integrated in the die area of 7.66 mm 2 by means of a 0.35m CMOS technology, with the dissipation of 146.60 mW from a single 3.3V supply.

show abstract

Section: Introductionmentioning

confidence: 99%