A Processor Extension for Time-Predictable Code Execution

A “New Ara” for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design

“…1 summarizes the SoA of the RISC-V-based processors, which have been developed by companies as well as researchers. Ara2 is the first processor that supports RVV 1.0 (Vicuna [9] does not implement the floating-point and is only compliant with the Zve32x subset). Among these vector architectures, [6], [8], [11], [12], [13], [14], are multi-core or multi-core-ready, testifying the interest of industry towards coupling the two paradigms.…”

“…The comparison with Vicuna [9] is especially hard since it is a 32-bit integer-only vector core. Its medium and fast configurations have the same computational capabilities, in terms of total throughput, of a 2-lane and 16-lane Ara2 systems.…”

“…RVV has reached frozen state with its 1.0 release in 2021 after six years of design and standardization efforts. Companies and academia developed numerous vector designs supporting various pre-release versions of RVV and targeting different application domains such as High-Performance Computing (HPC) [4], [5], [6], Deep Neural Networks (DNN) [7], AI/Augmented Reality (AR) [8], realtime applications [9], and Internet-of-Things (IoT) endpoints [10]. These designs are characterized by their heterogeneity in terms of deployed system architectures: [4], [5], [9], [11] are single-core systems, while [8], [10], [12], [13] are multicore or multi-core-ready.…”

“…Companies and academia developed numerous vector designs supporting various pre-release versions of RVV and targeting different application domains such as High-Performance Computing (HPC) [4], [5], [6], Deep Neural Networks (DNN) [7], AI/Augmented Reality (AR) [8], realtime applications [9], and Internet-of-Things (IoT) endpoints [10]. These designs are characterized by their heterogeneity in terms of deployed system architectures: [4], [5], [9], [11] are single-core systems, while [8], [10], [12], [13] are multicore or multi-core-ready. Among them, [4], [9], [12] work with a relatively simple in-order core, while [5], [8], [10], [11], [13], [14] deploy more aggressive superscalar or out-of-order scalar pipelines.…”

“…These designs are characterized by their heterogeneity in terms of deployed system architectures: [4], [5], [9], [11] are single-core systems, while [8], [10], [12], [13] are multicore or multi-core-ready. Among them, [4], [9], [12] work with a relatively simple in-order core, while [5], [8], [10], [11], [13], [14] deploy more aggressive superscalar or out-of-order scalar pipelines.…”