A Probabilistic Tabu Search State Assignment Algorithm for Area and Power Optimization of Sequential Circuits

El-Maleh, Aiman H.

doi:10.1007/s13369-020-04697-y

Cited by 13 publications

(10 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Let us indicate only some examples of articles and monographs, where the library [56] is used in experimental research. Such works include, for example, articles [31,35,52,[57][58][59] and monographs [6,39]. The basic characteristics of benchmarks are shown in Table 7.…”

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Improving Hardware in LUT-Based Mealy FSMs

2022

View full text Add to dashboard Cite

The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs) for representing both FSM state variables and outputs. The interstate transitions are represented by output collections generated during two adjacent cycles of FSM operation. To avoid doubling the number of variables encoding of COs, two registers are used. The first register keeps a code of CO produced in the current cycle of operation; the code of a CO produced in the previous cycle is kept in the second register. There is given a synthesis example with applying the proposed method. The results of the research are shown. The research is conducted using the CAD tool Vivado by Xilinx. The experiments prove that the proposed approach allows reducing the hardware compared with such known methods as auto and one-hot of Vivado, and JEDI. Additionally, the proposed approach gives better results than a method based on the simultaneous replacement of inputs and encoding of COs. Compared to circuits of the three-block FSMs, the LUT counts are reduced by an average of 7.21% without significant reduction in the performance. Our approach loses in terms of power consumption (on average 9.62%) and power–time products (on average 10.44%). The gain in LUT counts and area–time products increases with the increase in the numbers of FSM states and inputs.

show abstract

Section: Resultsmentioning

confidence: 99%

“…However, there are up to six address inputs in the present-day LUTs [19,33,34]. To balance the area-spatial-power characteristics of a LUT, it is necessary that the number of inputs does not exceed six [35]. Nevertheless, the total number of inputs and state variables of an FSM can significantly exceed the value of I.…”

Section: Related Workmentioning

confidence: 99%

Improving Hardware in LUT-Based Mealy FSMs

2022

View full text Add to dashboard Cite

show abstract

“…These methods should be applied if the number of arguments N A(φ i ) exceeds the value of N I LUT at least for a single function φ i ∈ D ∪ O [5]. These methods can improve either the LUT count or the maximum operating frequency or the consumed power [31]. Sometimes, these methods try to find a solution when more than a single characteristic is optimized.…”

Section: Related Workmentioning

confidence: 99%

Improving Characteristics of LUT-Based Sequential Blocks for Cyber-Physical Systems

2022

View full text Add to dashboard Cite

A method is proposed for optimizing circuits of sequential devices which are used in cyber-physical systems (CPSs) implemented using field programmable gate arrays (FPGAs). The optimizing hardware is a very important problem connected with implementing digital parts of CPSs. In this article, we discuss a case when Mealy finite state machines (FSMs) represent behaviour of sequential devices. The proposed method is aimed at optimization of FSM circuits implemented with look-up table (LUT) elements of FPGA chip. The method aims to reduce the LUT count of Mealy FSMs with extended state codes. The method is based on finding a partition of the set of internal states by classes of compatible states. To reduce LUT count, we propose a special kind of state codes named composite state codes. The composite codes include two parts. The first part includes the binary codes of states as elements of some partition class. The second part consists of the code of corresponding partition class. Using composite state codes allows us to obtain FPGA-based FSM circuits with exactly two levels of logic. If some conditions hold, then any FSM function from the first level is implemented by a single LUT. The second level is represented as a network of multiplexers. Each multiplexer generates either an FSM output or input memory function. An example of synthesis is shown. The experiments prove that the proposed approach allows us to reduce hardware compared with two methods from Vivado, JEDI-based FSMs, and extended state assignment. Depending on the complexity of an FSM, the LUT count is reduced on average from 15.46 to 68.59 percent. The advantages of the proposed approach grow with the growth of FSM complexness. An additional positive effect of the proposed method is a decrease in the latency time.

show abstract

“…There is M 1 = M 2 = 3 in the discussed case. Using (8) gives R(S 1 ) = R(S 2 ) = 2. As follows from the analysis of Table 1, the following sets exist for each class S k ∈ π S :…”

Section: Example Of Synthesismentioning

confidence: 99%

“…Three main characteristics determine the quality of an FSM circuit: the chip area occupied by the circuit, performance (either minimum propagation time or maximum operating frequency), and the consumption of power. These characteristics are strongly interconnected [8]. As a rule, the occupied chip area significantly affects other characteristics of an FSM circuit [9,10].…”

Section: Introductionmentioning

confidence: 99%

Improving Characteristics of LUT-Based Mealy FSMs with Twofold State Assignment

et al. 2021

View full text Add to dashboard Cite

Practically, any digital system includes sequential blocks. This article is devoted to a case when sequential blocks are represented by models of Mealy finite state machines (FSMs). The performance (maximum operating frequency) is one of the most important characteristics of an FSM circuit. In this article, a method is proposed which aims at increasing the operating frequency of LUT-based Mealy FSMs with twofold state assignment. This is done using only extended state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed approach leads to LUT-based Mealy FSM circuits having two levels of logic blocks. Each function for any logic level is represented by a circuit including a single LUT. The proposed method is illustrated by an example of synthesis. The results of experiments conducted with standard benchmarks show that the proposed approach produces LUT-based circuits with significantly higher operating frequency than it is for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, twofold state assignment). The performance is increased by an average of 15.9 to 25.49 percent. These improvements are accompanied by a small growth of the numbers of LUTs compared with circuits based on twofold state assignment. Our approach provides the best area-time products compared with other investigated methods. The advantages of the proposed approach increase as the number of FSM inputs and states increases.

show abstract

A Probabilistic Tabu Search State Assignment Algorithm for Area and Power Optimization of Sequential Circuits

Cited by 13 publications

References 22 publications

Improving Hardware in LUT-Based Mealy FSMs

Improving Hardware in LUT-Based Mealy FSMs

Improving Characteristics of LUT-Based Sequential Blocks for Cyber-Physical Systems

Improving Characteristics of LUT-Based Mealy FSMs with Twofold State Assignment

Contact Info

Product

Resources

About