A predictive physical model for hot-carrier degradation in ultra-scaled MOSFETs

Tyaginov, Stanislav; Bina, M.; Franco, J.; Wimmer, Yannick; Osintsev, Dmitri; Kaczer, B.

doi:10.1109/sispad.2014.6931570

Cited by 23 publications

(23 citation statements)

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“…In comparison to these cases, Channel Hot Carrier (CHC) degradation is inherently more complex [3,4]. CHC stress is non-uniform, with large currents present, and the resulting degradation is typically localized at the drain, thus offering a wider range of variability sources, as well as potential measurement artifacts.…”

Section: Visiting Imec From Ljmumentioning

confidence: 99%

Origins and implications of increased channel hot carrier variability in nFinFETs

Kaczer

Franco

Cho

et al. 2015

2015 IEEE International Reliability Physics Symposium

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visiting imec from LJMUOf the MOSFET degradation mechanisms, the variability of Time-Dependent Dielectric Breakdown (TDDB) and Bias Temperature Instability (BTI) in deeply scaled devices has been described with a degree of success [1,2]. In comparison to these cases, Channel Hot Carrier (CHC) degradation is inherently more complex [3,4]. CHC stress is non-uniform, with large currents present, and the resulting degradation is typically localized at the drain, thus offering a wider range of variability sources, as well as potential measurement artifacts. Variability of CHC degradation has been reported previously, mainly in planar devices [5][6][7][8][9]. Here we reexamine this topic in two generations of nFinFET devices and observe that CHC variability is generally higher than that of BTI, flagging it as the main contributor to time-dependent variability of FinFETs [10]. We examine in detail several intrinsic (random) and extrinsic (process-induced, systematic) sources of this increased variability. To aid this procedure, we demonstrate that matching pairs [7] can be used to eliminate extrinsic (process-related) time-dependent variability sources, analogously to time-0 variation [11]. We discuss the intrinsic variability sources in the defect centric framework [2,12] and provide a blueprint for projecting CHC variability to operating conditions and lifetimes. A population of nFinFET devices with (as drawn) gate lengths L G ranging from 130 nm down to 28 nm, fin height ~30 nm, highk gates, fabricated in two imec technologies, distributed across wafer, have been subjected to either CHC or PBTI stress at either RT or 125 o C. An example of the increased spread of CHC degradation wrt BTI for the same mean threshold voltage shift ΔV th  is in Fig. 1. In the following we quantify the variability in terms of average charged trap impact η = σ ΔVth 2 /(2ΔV th ) (eq. 1), a crucial defect-centric parameter [2,13]. We first identify several potential sources of this increased CHC variability (Fig. 2). Since the CHC energy distribution is an intricate function of the electric field distribution in the device body, a dependence on device length (Fig. 2a) and biases (Fig. 2b) variations can be expected. From CHC ΔV th  vs L g dependence (not shown) we can readily extract the effect's sensitivity to channel L g variation to be (technology dependent) ~2.5 mV/nm. With this in mind and assuming σ Leff = 2 nm, η = 0.13 mV (cf. Eq. 1), suggesting this mechanism is not the main contributor to CHC variability. Fig. 3 illustrates the sensitivity of CHC energy distribution at the drain to the drain bias V D . Again from measurements of CHC ΔV th  vs. V D (not shown) we can conclude that η is negligible 0.07 mV for σ VD = 10 mV, however, η is considerable 2.2 mV for σ VD = 50 mV. Setting aside circuit implications of varying V D for the moment, we conclude that variations in source/drain series resistance (Fig. 2b) could be responsible for the increased CHC variability. We, however, observe no correlation between channel current d...

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Section: Visiting Imec From Ljmumentioning

confidence: 99%

Origins and implications of increased channel hot carrier variability in nFinFETs

Kaczer

Franco

Cho

et al. 2015

2015 IEEE International Reliability Physics Symposium

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“…At the microscopic level, we model the two competing mechanisms of bond dissociation, namely, the single-and multiple-carrier processes [11], [12], [25]- [30]. These processes are considered consistently as two competing pathways of the same bond dissociation reaction [11], [12], [30]. The rates of these processes are determined by the carrier energy DF, which has to be calculated for a given transistor topology and defined stress/operating conditions.…”

Section: Simulation Frameworkmentioning

confidence: 99%

“…Although the first method was extensively used in the first versions of our HCD model [14], [15], [39], the Monte Carlo approach is not well suited for HCD modeling in LDMOS devices due its enormous computational demands related to resolving the high-energy tails. Thus, our model is implemented in our deterministic BTE solver ViennaSHE [11], [12], [30]. An alternative way, as mentioned before, is to use simplified approaches to the BTE solution such as the DD scheme.…”

Section: B Carrier Transportmentioning

confidence: 99%

“…The carrier DFs are used to compute the carrier acceleration integral (AI), which determines the rates of both single-and multiple-carrier processes [11], [12], [30] …”

Section: Interface State Generation Kineticsmentioning

confidence: 99%

“…A remedy can be a physical HCD model that covers the whole hierarchy of the aspects related to HCD, namely, 1) a thorough carrier transport treatment that provides the information on the carrier energy distribution function needed to 2) model the microscopic mechanism of trap generation and the corresponding rates, and to 3) simulate the characteristics of the degraded devices [11], [12]. The most computationally expensive among these subtasks is the carrier transport treatment, which requires a solution of the Boltzmann transport equation (BTE).…”

Section: Introductionmentioning

confidence: 99%

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Modeling of Hot-Carrier Degradation in nLDMOS Devices: Different Approaches to the Solution of the Boltzmann Transport Equation

Sharma

Tyaginov

Wimmer

et al. 2015

IEEE Trans. Electron Devices

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We propose two different approaches to describe carrier transport in n-laterally diffused MOS (nLDMOS) transistor and use the calculated carrier energy distribution as an input for our physical hot-carrier degradation (HCD) model. The first version relies on the solution of the Boltzmann transport equation using the spherical harmonics expansion method, while the second uses the simpler drift-diffusion (DD) scheme. We compare these two versions of our model and show that both approaches can capture HCD. We, therefore, conclude that in the case of nLDMOS devices, the DD-based variant of the model provides good accuracy and at the same time is computationally less expensive. This makes the DD-based version attractive for predictive HCD simulations of LDMOS transistors.Index Terms-Drift-diffusion (DD) scheme, hot-carrier degradation (HCD), n-laterally diffused MOS (nLDMOS), spherical harmonics expansion (SHE).

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Physics-Based Modeling of Hot-Carrier Degradation

Tyaginov

2014

Hot Carrier Degradation in Semiconductor Devices

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A predictive physical model for hot-carrier degradation in ultra-scaled MOSFETs

Cited by 23 publications

References 10 publications

Origins and implications of increased channel hot carrier variability in nFinFETs

Origins and implications of increased channel hot carrier variability in nFinFETs

Modeling of Hot-Carrier Degradation in nLDMOS Devices: Different Approaches to the Solution of the Boltzmann Transport Equation

Physics-Based Modeling of Hot-Carrier Degradation

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