A Predictive Flow Control Scheme for Efficient Network Utilization and QoS

Qiu, Dongyu; Shroff, Ness B.

doi:10.1109/tnet.2003.822638

Cited by 22 publications

(14 citation statements)

References 16 publications

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“…channel bandwidth, buffer capacity and control state, are allocated to packets traversing a network. A decentralized control system and a predictive explicit-rate control are developed in [12,13]. A predictive flow controller that controls the packet injection rate is proposed in [14].…”

Section: Related Workmentioning

confidence: 99%

An SDRAM-Aware Router for Networks-on-Chip

Jang

Pan

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In this paper, we present an NoC (Networks-on-Chip) router with an SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilization and reduce memory latency. Moreover, our multi-scheduling scheme performed by the multiple SDRAM-aware routers helps to achieve better SDRAM performance and save the hardware cost of NoC platform. Experimental results show that our SDRAMaware router improves memory latency by 18% and memory utilization by 4.9% on average with over 42% saving of gate count of the NoC platform with dual memory subsystem.

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Section: Related Workmentioning

confidence: 99%

An SDRAM-Aware Router for Networks-on-Chip

Jang

Pan

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Indeed, based on our idea, any deterministic and adaptive routing scheme can be combined to form our SDRAMaware router. Another flow-control mechanism mentioned in section 2 can also be combined to avoid deadlock and livelock [17], to make traffic load balanced on a network [12][13][14] and to manage buffers and channel bandwidth [15].…”

Section: Sdram-aware Noc Routermentioning

confidence: 99%

An SDRAM-aware router for Networks-on-Chip

Jang

Pan

2009

Proceedings of the 46th Annual Design Automation Conference

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“…A comparison of the overhead of flow control algorithms can be found in [15]. Congestion control is well studied for macronetworks [2,6,12,17]. In [12], the authors develop a decentralized control system, where the sources adjust their traffic generation rates based on the feedback received from the bottleneck links.…”

Section: Related Work and Paper Contributionmentioning

confidence: 99%

Prediction-based flow control for network-on-chip traffic

Ogras

Mărculescu

2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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Networks-on-Chip (NoC) architectures provide a scalable solution to on-chip communication problem but the bandwidth offered by NoCs can be utilized efficiently only in presence of effective flow control algorithms. Unfortunately, the flow control algorithms published to date for macronetworks, either rely on local information, or suffer from large communication overhead and unpredictable delays. Hence, using them in the NoC context is problematic at best. For this reason, we propose a predictive closed-loop flow control mechanism and make the following contributions: First, we develop traffic source and router models specifically targeted to NoCs. Then, we utilize these models to predict the cases of possible congestion in the network. Based on this information, the proposed scheme controls the packet injection rate at traffic sources in order to regulate the total number of packets in the network. Evaluations involving real and synthetic traffic patterns show that the proposed controller delivers a superior performance compared to the traditional switch-to-switch flow control algorithms.

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A Predictive Flow Control Scheme for Efficient Network Utilization and QoS

Cited by 22 publications

References 16 publications

An SDRAM-Aware Router for Networks-on-Chip

An SDRAM-Aware Router for Networks-on-Chip

An SDRAM-aware router for Networks-on-Chip

Prediction-based flow control for network-on-chip traffic

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