A Predetermined LMS Digital Background Calibration Technique for Pipelined ADCs

Montazerolghaem, Mohammad Ali; Moosazadeh, Tohid; Yavari, Mohammad

doi:10.1109/tcsii.2015.2435071

Cited by 18 publications

(8 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Al propose a digital background calibration technique with LMS algorithm to righteous the capacitor mismatch and error gains in which the conversion time is significantly reduced as compared to the same LMS techniques used in the other publication in the year 2014 by B. Zenali. The technique was simulated on 12-bit 100MS/s spilt pipelined ADC [14]. Another work attained shorter calibration times for split pipelined ADC and handled the non-orthogonality's of calibration loop.…”

Section: Figmentioning

confidence: 99%

Analog to Digital Converters (ADC): A Literature Review

Dalmia

Sinha

2020

E3S Web Conf.

View full text Add to dashboard Cite

The signal processing is advancing day by day as its needs and in wireline/wireless communication technology from 2G to 4G cellular communication technology with CMOS scaling process. In this context the high-performance ADCs, analog to digital converters have snatched the attention in the field of digital signal processing. The primary emphasis is on low power approaches to circuits, algorithms and architectures that apply to wireless systems. Different techniques are used for reducing power consumption by using low power supply, reduced threshold voltage, scaling of transistors, etc. In this paper, we have discussed the different types and different techniques used for analog to digital conversion of signals considering several parameters.

show abstract

Section: Figmentioning

confidence: 99%

Analog to Digital Converters (ADC): A Literature Review

Dalmia

Sinha

2020

E3S Web Conf.

View full text Add to dashboard Cite

show abstract

“…Therefore, the input–output characteristic of residue amplifier is approximated by a third-order Taylor series polynomial, and neglecting higher-order terms as follows (Sahoo and Razavi, 2009; Panigada and Galton, 2009): where V res , V x and α 3 denote the output residue voltage, the input residue voltage and third-order nonlinearity of the residue amplifier, respectively. Furthermore, α 1 is defined as follows (Sahoo and Razavi, 2009; Montazerolghaem et al , 2015): where A represents finite DC gain and C s /C F is defined as follows: where δ represents the capacitor mismatch (Zeinali et al , 2014). Therefore, α 1 shows the capacitor mismatch together with finite DC gain of the residue amplifier.…”

Section: Pipelined Analog-to-digital Converter Architecture Multiplying Digital-to-analog Converter Modelingmentioning

confidence: 99%

“…The normal operation of the pipelined ADCs is interrupted in foreground calibrations while background techniques continuously detects and removes the errors. The most popular digital background calibration methods are categorized into histogram-based (Brooks and Lee, 2008; Gholami and Yavari, 2017), statistical-based (Mafi et al , 2018; Mafi et al , 2016), correlation-based (Panigada and Galton, 2006; Panigada and Galton, 2009) and deterministic (McNeill et al , 2009; Sarkar et al , 2015; Sehgal et al , 2015; Montazerolghaem et al , 2015; Zia et al , 2019). The priority of deterministic techniques over others is the faster calibration time.…”

Section: Introductionmentioning

confidence: 99%

New digital background calibration method for pipelined ADCs

Zia

Farshidi

Kosarian

2020

COMPEL

View full text Add to dashboard Cite

Purpose Pipelined analog-to-digital converters (ADCs) are widely used in electronic circuits. The purpose of this paper is to propose a new digital background calibration method to correct the capacitor mismatch, finite direct current (DC) gain and nonlinearity of residue amplifiers in pipelined ADCs. Design/methodology/approach The errors are corrected by defining new functions based on generalized Newton–Raphson algorithm. Although the functions have analytical solutions, an iterative procedure is used for calibration. To accelerate the calibration process, proper initialization for the errors is identified by using evaluation estimation block and solving inverse matrix. Findings Several behavioral simulations of a 12-bit 100MS/s pipelined ADC in MATLAB indicate that signal-to-(noise + distortion) ratio (SNDR) and spurious free dynamic range (SFDR) are improved from 30dB/33dB to 70dB/79dB after calibration. Calibration is achieved in approximately 2,000 clock cycles. Practical implications The digital part of the proposed method is implemented on field-programmable gate array to validate the performance of the pipelined ADC. The experimental result shows that the degradation of SNDR, SFDR, integral nonlinearity, differential nonlinearity and effective number of bits is negligible according to fixed-point operation vs floating-point in simulation results. Originality/value The novelty of this study is to use Newton–Raphson algorithm combined with appropriate initialization to reduce the number of divisions as well as calibration time, which is suitable in the recent nano-meter complementary metal oxide semiconductor technologies.

show abstract

“…when the output voltage reaches its final value. Therefore according to Equation 5, Equations (15)- (17), and Equation 19, we can obtain the following simplified Equations 20…”

Section: Input Cls-based Offset and Finite-gain Compensated Sc Amplifiermentioning

confidence: 99%

“…Recently, several techniques have been developed to alleviate the finite gain error of op-amps in SC circuits, such as comparator-based SC (CBSC) circuits [11,12], digital circuits-based SC circuits, which are also called zero-crossing-detectors-based (ZCD) SC circuits [13][14][15] and digital calibration algorithms [16][17][18]. However, CBSC circuits introduce large offset errors and linearity problems due to the output overshoots and voltage drop on switches [19].…”

Section: Introductionmentioning

confidence: 99%

A Novel Offset and Finite-Gain Compensated Switched-Capacitor Amplifier with Input Correlated Level Shifting

Chen

Guo³

et al. 2019

Electronics

View full text Add to dashboard Cite

A novel offset and finite-gain compensated differential switched-capacitor(SC) amplifier is presented. Incorporating the correlated double sampling (CDS) technique and input correlated level shifting (CLS) technique together, the DC offset and DC gain error of SC amplifier are further reduced by a factor of op-amp DC gain compared with the conventional offset and finite-gain compensated SC amplifier. The effectiveness of the new scheme has been analyzed and verified by extensive simulations. An SC amplifier with the proposed scheme is designed in 130 nm CMOS technology. Simulated results show that with an op-amp having a low DC gain of 30 dB and an input offset of 10 mV, the proposed SC amplifier achieves an output offset and DC-gain error of 154 µV and 0.05%, respectively, which are significantly improved compared with 1.155 mV and 0.42% achieved in the conventional SC amplifier.

show abstract

A Predetermined LMS Digital Background Calibration Technique for Pipelined ADCs

Cited by 18 publications

References 9 publications

Analog to Digital Converters (ADC): A Literature Review

Analog to Digital Converters (ADC): A Literature Review

New digital background calibration method for pipelined ADCs

A Novel Offset and Finite-Gain Compensated Switched-Capacitor Amplifier with Input Correlated Level Shifting

Contact Info

Product

Resources

About