A Pre-Bootstrapping Method for Use in Gate Driver Circuits to Improve the Scan Pulse Delay of High-Resolution TFT-LCD Systems

Lin, Chih‐Lung; Deng, Ming-Yang; Chiu, Wen-Ching; Shih, Li-Wei; Chang, Jui‐Hung; Lin, Yu-Sheng; Lee, Ching-En

doi:10.1109/tie.2019.2940000

Cited by 10 publications

(12 citation statements)

References 29 publications

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“…The loading of the clock bus lines is 1.54 k and 133.5 pF. Also, eight clocks are placed equally on both sides of the panel to support the pre-charging method [17]. The pulse width and duty ratio of the clock signals are thus set to 20 µs (5.75 µs ×4−3µs) and 43.5% (20 µs/ 46 µs ×100%), respectively.…”

Section: Resultsmentioning

confidence: 99%

“…Moreover, the clock-feed-through effect of parasitic capacitors is suppressed to prevent the non-output stages of the gate driver from producing leakage currents that cause the delays in the clock signals. Experimental results indicate that the proposed circuit can effectively yield a shorter rising time of the scan pulse compared with the previously developed work [17]. Fig.…”

Section: Introductionmentioning

confidence: 80%

“…The reduction in the leakage current of the pull-down structure, however, is inadequate for use in highresolution or high-frame-rate displays when the operating frequency of the gate driver increases. In contrast, the capacitive coupling method [16], [17], which raises the driving current of the driving TFT by increasing its gate-to-source voltage (V GS ), can greatly improve the driving capability of the gate driver. Since this method uses the capacitive coupling effect to bootstrap the voltage at the gate node of the driving TFT, the parasitic capacitances must be considered in the circuit design.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Low-Leakage Capacitive Coupling Structure for a-Si:H Gate Driver With Less Delay of Clock Signals Used in AMLCDs

Deng

Liao

Chen

et al. 2020

IEEE J. Electron Devices Soc.

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This work proposes a hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) gate driver with a low-leakage capacitive coupling structure to reduce the delay of the clock signal. The proposed circuit suppresses the fluctuation in the gate node of the driving TFT induced by clock-feedthrough effect, reducing the leakage current that flows from the clock signal line to the power source line with a low voltage level. This reduction in the leakage current can improve the degradation in the voltage of the clock signal and thus avoid the increase in the rising time of the scan pulse. Measurements for extracting the drain current versus gate-to-source voltage (I D-V GS) curves of a fabricated a-Si:H TFT are made to establish a simulation TFT model by fitting the obtained curves. For the same parameters of the TFTs and capacitances, the leakage current and the rising time of the output waveform of the proposed circuit are 45.45% and 21.36% lower, respectively, than those of previously developed gate driver. INDEX TERMS a-Si:H TFTs, capacitive-coupling effect, clock-feed-through effect, gate driver, leakage current.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 80%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Low-Leakage Capacitive Coupling Structure for a-Si:H Gate Driver With Less Delay of Clock Signals Used in AMLCDs

Deng

Liao

Chen

et al. 2020

IEEE J. Electron Devices Soc.

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“…Take previous studies, [15][16][17][18][19][20][21] for example. The former structure uses the DC voltage collocated with diode-connecting TFT, 15,21 and the latter structure uses coupling signal of driving clock [16][17][18][19][20] to charge the low-level holding TFTs like T7, T8, T14, and T15 for preventing the noise. In Hu et al, 15 the bipolar pulses and two replicated noise-free blocks are used to reach full-time noise free and F I G U R E 1 Gate driver with parallel bipolar pulses noise-free block 15…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, decreasing the fabrication cost is one of the most important demand for the display market. As a result, the integrated gate driver 1–21 based on amorphous silicon thin‐film transistors (a‐Si TFTs) has become a main stream in generation of display nowadays because it provides many advantages including reduction in the cost by eliminating external driver ICs and bonding connections, improvement on compactness and reliability, and simplification of data driver configuration.…”

Section: Introductionmentioning

confidence: 99%

High‐reliability gate driver on array using noise sharing of precharging node for thin film transistor–liquid crystal display application

Zheng

Liu

et al. 2020

J Soc Info Display

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A hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) gate driver with negative bias stress on precharging node for noise sharing with high-reliability 10.7-in. automotive display has been proposed. The proposed circuit is composed of precharging block, pull-up and pull-down block, and noise-free block. The precharging block not only starts up the gate driver but also reduces noise with 33% duty cycle. Duplicate output signals are responsible for turning on next stage to decrease the loading of output of gate line. Moreover, negative bias voltage recovering of TFTs could be created by setting another lower voltage source to lower the threshold voltage degradation of TFTs. According to lifetime test results, the proposed gate driver of 708 stages passes the extreme temperature range test (90 C and −40 C) for simulation and −40 C for measurement and remains stable over 800 h at 90 C test. Finally, this design is successfully demonstrated in a 10.7-in. HD (1280 × RGB × 720) TFT-LCD panel.

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Highly reliable a‐Si:H gate driver on array with complementary double‐sided noise‐eliminating and dual voltage levels for TFT‐LCD applications

Zheng,

Liu,

Chen

et al. 2023

J Soc Info Display

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In this work, we present a high‐reliability gate driver on array (GOA) for a 10.7‐in. HD (1,280 × RGB × 720) TFT‐LCD panel, featuring an alternatively double‐sided noise‐eliminating function. The gate driver circuit is designed with 12‐phase clock signals that exhibit 75% signal overlapping, threshold voltage recovering, and double‐sided driving schemes. The double‐sided driving scheme reduces the number of mental wires and TFTs in the gate driver circuit, resulting in a smaller layout area for GOA. By utilizing dual levels of voltage, we implemented a negative gate bias method to mitigate threshold voltage shifts for the noise‐eliminating and driving TFTs. This prevents the noises from clock signals effectively. The reliability test of the proposed GOA with 720 stages passed a strict testing condition (90°C and −40°C) for simulation and exhibited good performance over 800 hours at 90°C for measurement.

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A Pre-Bootstrapping Method for Use in Gate Driver Circuits to Improve the Scan Pulse Delay of High-Resolution TFT-LCD Systems

Cited by 10 publications

References 29 publications

Low-Leakage Capacitive Coupling Structure for a-Si:H Gate Driver With Less Delay of Clock Signals Used in AMLCDs

Low-Leakage Capacitive Coupling Structure for a-Si:H Gate Driver With Less Delay of Clock Signals Used in AMLCDs

High‐reliability gate driver on array using noise sharing of precharging node for thin film transistor–liquid crystal display application

Highly reliable a‐Si:H gate driver on array with complementary double‐sided noise‐eliminating and dual voltage levels for TFT‐LCD applications

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