A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop

Wang, Chua-Chin; Chien, Yu-Tsun; Chen, Ying-Pei

doi:10.1109/iscas.1999.780798

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

DOI: 10.1109/iscas.1999.780798

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A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop

Chua-Chin Wang

Yu-Tsun Chien²,

Ying-Pei Chen³

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Cited by 1 publication

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A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop

Cited by 1 publication

References 7 publications

A 1.0 GHz clock generator design with a negative delay using a single-shot locking method

A 1.0 GHz clock generator design with a negative delay using a single-shot locking method

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