2007
DOI: 10.1109/tcapt.2007.897977
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A Practical Implementation of Silicon Microchannel Coolers for High Power Chips

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Cited by 192 publications
(38 citation statements)
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“…Alternative solutions such as jet impingement cooling, single-phase and two-phase cooling in microchannels have been explored and showed different advantages or drawbacks (e.g. Agostini et al [2], Colgan et al [12] and Faulkner et al [15]). Among them, two-phase flow boiling in microchannels seems to be the most promising approach.…”
Section: Introductionmentioning
confidence: 99%
“…Alternative solutions such as jet impingement cooling, single-phase and two-phase cooling in microchannels have been explored and showed different advantages or drawbacks (e.g. Agostini et al [2], Colgan et al [12] and Faulkner et al [15]). Among them, two-phase flow boiling in microchannels seems to be the most promising approach.…”
Section: Introductionmentioning
confidence: 99%
“…However, recent data obtained with enhanced single-phase flow and flow boiling in microchannels indicate that this may not be necessarily true with the current status of these two modes of heat transfer. Single-phase in enhanced microchannels, 48 µm×256 µm, offset strip fins, 500 µm, Colgan et al (2007), Steinke and Kandlikar (2006) > 500 5-10…”
Section: Introductionmentioning
confidence: 99%
“…However, the microchannels enhanced with short offset strip fins provide a very high heat transfer coefficient. In a practical system with this geometry, Colgan et al (2007) employed multiple inlet/outlet regions with a flow length of only 2 mm through the microchannels. This configuration holds the most promise in meeting the future chip cooling challenges.…”
Section: Introductionmentioning
confidence: 99%
“…Because of close placement of chips on the silicon carrier, heat removal may become an issue for chips dissipating large amount of power. However, latest development in thermal interface materials and copper heat sinks coupled with micro-channel liquid cooling assure heat removal capability of greater than 300 W/cm 2 [3]. Additionally, chips that are assembled on the silicon carrier can be thinned down to the same thickness using well developed wafer thinning technologies [9].…”
Section: Eda Issuesmentioning
confidence: 99%