A practical approach to instruction-based test generation for functional modules of VLSI processors

Hatayama, Kazumi; Hikone, Kazunori; Miyazaki, T.; Yamada, H.

doi:10.1109/vtest.1997.599436

Cited by 4 publications

(2 citation statements)

References 15 publications

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“…In the last decade, software-based self-testing (SBST) techniques are specially considered for in-field testing of processing cores in safety-critical systems [3][4][5][6][7]. In SBST techniques, a processor is tested using a sequence of its native instructions.…”

Section: Introductionmentioning

confidence: 99%

HASTI: hardware‐assisted functional testing of embedded processors in idle times

Kamran

2019

IET Computers & Digital Techniques

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In the past decades, software-based self-testing (SBST) which is testing of a processing core using its native instructions has attracted much attention. However, efficient SBST of a processing core which is deeply embedded in a multicore architecture is still an open issue. In this study, inspiring from built-in self-test methods, the authors place several number of hardware test components next to the processing cores in order to overcome existing SBST challenges. These test components facilitate quick testing of embedded cores by providing several mechanisms such as virtual fetch, virtual jump, fake load & store, and segmented test application. In order to enable segmented test application, they propose the concept of test snippet and a test snippet generation approach. The result is the capability of testing embedded cores in short idle times leading to efficient online testing of the cores with zero performance overhead. The authors' results show that their test snippet generation approach not only leads to the production of test snippets which are properly fitted the proposed test architecture but also its final fault coverage is comparable and even a little better than the fault coverage of the best existing methods.

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Section: Introductionmentioning

confidence: 99%

HASTI: hardware‐assisted functional testing of embedded processors in idle times

Kamran

2019

IET Computers & Digital Techniques

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“…For instance, it is not possible to perform a shift operation on an FP register, a necessary operation when implementing a software-based pseudo-random number generator. FP unit testing using the processor's ISA has been studied in the past in [19], where the authors use an ATPG tool to create test patterns after describing the operational constraints imposed by the ISA to the FP unit. The reported fault coverage of double precision FP adder and multiplier saturates around 90 percent, a fact that shows the difficulty in testing of FP units as the precision increases.…”

Section: Introductionmentioning

confidence: 99%

Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units

Xenoulis

Gizopoulos

Psarakis

et al. 2009

IEEE Trans. Dependable and Secure Comput.

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Online periodic testing of microprocessors is a valuable means to increase the reliability of a low-cost system, when neither hardware nor time redundant protection schemes can be applied. This is particularly valid for floating-point (FP) units, which are becoming more common in embedded systems and are usually protected from operational faults through costly hardware redundant approaches. In this paper, we present scalable instruction-based self-test program development for both single and double precision FP units considering different instruction sets (MIPS, PowerPC, and Alpha), different microprocessor architectures (32/64-bit architectures) and different memory configurations. Moreover, we introduce bit-level manipulation instruction sequences that are essential for the development of FP unit's self-test programs. We developed self-test programs for single and double precision FP units on 32-bit and 64-bit microprocessor architectures and evaluated them with respect to the requirements of low-cost online periodic self-testing: fault coverage, memory footprint, execution time, and power consumption, assuming different memory hierarchy configurations. Our comprehensive experimental evaluations reveal that the instruction set architecture plays a significant role in the development of self-test programs. Additionally, we suggest the most suitable self-test program development approach when memory footprint or low power consumption is of paramount importance.

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Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units

Xenoulis

Psarakis

Gizopoulos

et al. 2006

IEEE Trans. Comput.

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A practical approach to instruction-based test generation for functional modules of VLSI processors

Cited by 4 publications

References 15 publications

HASTI: hardware‐assisted functional testing of embedded processors in idle times

HASTI: hardware‐assisted functional testing of embedded processors in idle times

Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units

Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units

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