A Power Efficient Reconfigurable Max-Log-MAP Turbo Decoder for Wireless Communication Systems

Han, Juan; Erdogan, A.T.; Arslan, Tughrul

doi:10.1109/socc.2005.1554504

Cited by 3 publications

(1 citation statement)

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“…A flexible max-log-MAP decoder with m max ¼ 4 is presented in [16]. The evaluation is carried out similar to [10], and hence the information about the introduced overhead does not cover aspects missing in Chadha's investigation.…”

Section: M-flexible Solutionsmentioning

confidence: 99%

Design and measurement of a variable-rate Viterbi decoder in 130-nm digital CMOS

Kamuf¹,

Rodrigues²,

Anderson³

et al. 2010

Microprocessors and Microsystems

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This paper discusses design and measurements of a flexible Viterbi decoder fabricated in 130-nm digital CMOS. Flexibility was incorporated by providing various code rates and modulation schemes to adjust to varying channel conditions. Based on previous trade-off studies, flexible building blocks were carefully designed to cause as little area penalty as possible. The chip runs down to a minimal core supply of 0.8 V. It turns out that striving for more modulation schemes is beneficial in terms of power consumption once the price is paid for accepting different code rates viz. radices in the trellis and survivor path units.

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Section: M-flexible Solutionsmentioning

confidence: 99%