A power efficient PFD-CP architecture for high speed clock and data recovery application

Maiti, Madhusudan; Saw, Suraj Kumar; Nath, Vijay; Majumder, Alak

doi:10.1007/s00542-019-04458-4

Cited by 10 publications

(4 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The performance comparison of the proposed FNPLL with other methods is given in Table 2. The proposed phase and frequency detector has the maximum switching frequency and is measured to be 3.5 GHz, by using the methodology given by Maiti et al (2019. The designed PFD is free from the reset path and consists of only Eight transistors such that the power consumption is of about 168.3 µW @ 3.5 GHz are shown in Figure 12.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

“…As per the literature considered, every proposed FNPLL is simulated for phase noise at frequency offsets (Maiti et al , 2019; Zhang et al , 2019) of 10 kHz, 100 kHz, and 1 MHz are –93.18, –101.4 and –117 dBc/Hz, respectively, is depicted in Figure 13. Table 3 shows the comparisons of the proposed frequency synthesizer with the recently published work.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

“…2. The proposed phase and frequency detector has the maximum switching frequency and is measured to be 3.5 GHz, by using the methodology given by Maiti et al (2019. The designed PFD is free from the reset path and consists of only Eight transistors such that the power consumption is of about 168.3 m W @ 3.5 GHz are shown in Figure 12. FNPLL architecture proposed is designed in 45 nm CMOS technology consumes 3.3 mW of power from 0.45 V supply.…”

Section: Proposed Lc-voltage Control Oscillatormentioning

confidence: 99%

“…Dead zone causes spurious tones and reference spurs which affects the spectrum of the FNPLL. The CP also causes the in-band noise (De Muer and Steyaert, 2002; Maiti et al , 2019) due to the mismatch of currents and interactions with the DDSM (De Muer and Steyaert, 2002; Arora et al , 2005; Maiti et al , 2019). By linearizing, the currents in the CP unfold the in-band noises in the DDSM and CP.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Efficient techniques of fractional-N PLL for pervasive wireless applications

Abdul

Nelakuditi

2022

IJPCC

View full text Add to dashboard Cite

Purpose The purpose of this paper to ensure the rapid developments in the radio frequency wireless technology, the synthesis of frequencies for pervasive wireless applications is crucial by implementing the design of low voltage and low power Fractional-N phase locked loop (PLL) for controlling medical devices to monitor remotely patients. Design/methodology/approach The developments urge a technique reliable to phase noise in designing fractional-N PLL with a new eight transistor phase frequency detector and a good linearized charge pump (CP) for speed of operation with minimum mismatches. Findings In applications for portable wireless devices, by proposing a new phase-frequency detector with the removal of dead, blind zones and a modified CP to minimize the mismatch of currents. Originality/value The results are simulated in 45 nm complementary metal oxide semiconductor generic process design kit (GPDK) technology in cadence virtuoso. The phase noise of the proposed Fractiona-N phase locked loop has–93.18, –101.4 and –117 dBc/Hz at 10 kHz, 100 kHz and 1 MHz frequency offsets, respectively, and consumes 3.3 mW from a 0.45 V supply.

show abstract

Section: Simulation Results and Discussionmentioning

confidence: 99%

Section: Simulation Results and Discussionmentioning

confidence: 99%

Section: Proposed Lc-voltage Control Oscillatormentioning

confidence: 99%