A Power-Efficient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain

Wu, Lianbo; Burger, Thomas; Schonle, Philipp; Huang, Qiuting

doi:10.1109/jssc.2020.3047431

Cited by 11 publications

(8 citation statements)

References 33 publications

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“…edges with an ADC [6], [46], [52]- [54] appears a promising solution, while its fractional-N operation may rely on a digitalto-time converter (DTC) [9], [10], [55]- [57] or DAC [5], [46], [53], [58]. Considering such a conceptual ADC-based TDC 'sampling' the oscillator's slope, its TDC gain, t tdc (unit: s/bit), is derived as…”

Section: ) Adc-based Tdcmentioning

confidence: 99%

Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial

Siriburanon

Staszewski

2022

IEEE Trans. Circuits Syst. II

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In this tutorial brief, we introduce a unified wideband phase-noise theory framework of frequency synthesis based on a multirate timestamp modeling with "two z-variables". We apply it to model and analyze two types of ultra-low jitter (i.e., sub-50 fs) phase-locking techniques: 1) high-bandwidth PLLs with high phase-detector gain (with emphasis on all-digital PLLs), and 2) injection locking (IL) or recently proposed charge-sharing locking (CSL), serving as a unified guide on achieving the sub-50 fs jitter. All analytical results are numerically verified through time-domain behavioral simulations, demonstrating that the theoretically maximum bandwidths are around 30% and 44% of the reference frequency in PLLs and IL, respectively.

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Section: ) Adc-based Tdcmentioning

confidence: 99%

Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial

Siriburanon

Staszewski

2022

IEEE Trans. Circuits Syst. II

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“…Essentially, it converts the time to voltage only once, simplifying the system structure and circuit implementation. A similar voltage-domain PD is also used in [40] to achieve an improved power-jitter tradeoff. However, to operate under the supply ripple, the loop in [40] and Fig.…”

Section: Proposed Dpll Architecturementioning

confidence: 99%

“…A similar voltage-domain PD is also used in [40] to achieve an improved power-jitter tradeoff. However, to operate under the supply ripple, the loop in [40] and Fig. 3(b) still needs to be further modified.…”

Section: Proposed Dpll Architecturementioning

confidence: 99%

“…Hence, the maximum voltage on the C SG and C DAC capacitors is limited to ∼V ref /2, providing enough voltage headroom for the PMOS current sources to operate linearly. In contrast, the DAC and slope generator in [40] sequentially charge the same capacitor to ∼V ref . This reduces the voltage headroom of the slope generator's current source, substantially degrading its linearity in a deep sub-micrometer technology with reduced supply.…”

Section: A Phase Detector 1) Operating Principlementioning

confidence: 99%

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A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <−54-dBc Spurs Under 50-mVpp Supply Ripple

Chen

Gong

Staszewski

et al. 2022

IEEE J. Solid-State Circuits

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In this article, we present a 4.5-5.1-GHz fractional-N digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc-dc converter. Supply pushing of its inductor-capacitor (LC) oscillator is suppressed by properly replicating the supply ripple onto the gate of its tail current transistor, while the optimum replication gain is determined by a new on-chip calibration loop tolerant of supply variations. A proposed configuration of cascading a supply-insensitive slope generator with an output of a current digital-to-analog converter (DAC) linearly converts the phase error timing into a corresponding voltage, which is then quantized by a successive approximation register (SAR) analog-to-digital converter (ADC) to generate a digital phase error. We also introduce a low-power ripple pattern estimation and cancellation algorithm to remove the phase error component due to the supply-induced delay variations of loop components. Implemented in 40-nm CMOS, the DPLL prototype achieves the performance of 428-fs rms jitter, <−55-dBc fractional spur, and <−54-dBc maximum spur while consuming 3.25 mW and being subjugated to a sinusoidal or sawtooth supply ripple of 50 mV pp at 50-MHz reference divided by 3, 6, or 12.

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“…In the past decades, clock is mostly used in the fixedfrequency style with high-frequency-stability as its highest priority. In clock-circuit design, people have focused almost their full attention on minimizing clock jitter and lowering phase noise [1][2][3][4][5][6][7][8][9]. When used in applications, such clock signal however has only few useable frequency choices.…”

Section: Introductionmentioning

confidence: 99%

A New Perspective of Flexible Clocking Ideology for Driving and Devising Circuits in Emerging Resource-Constrained Applications

Wei

Xiu

2022

IEEE Access

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Clock is the most important signal in electronic system. In current practice, the dominant clocking style is the fixed-frequency approach. For a given application, the clock signal is only required to work at a few selected frequencies. Moreover, in the process of performing a task, it must not change its frequency. This style has worked well in the past. However, it is preventing information processing efficiency from being raised to next level. Worse yet, the emergence of resource-constrained applications, such as edge computing and IoT, can render this approach unserviceable. In this paper, a new perspective of flexible clocking ideology is advocated. It promotes the use of a clock generator, TAF-DPS, that possesses features of "arbitrary frequency generation" and "instantaneous frequency switching". Owing to its superior capability in synthesizing waveform, TAF-DPS can handle many signal processing problems in a more elegant manner and serve some special purposes more efficiently. Further, it can be used for generating data for security purposes. TAF-DPS is especially applicable for environments with large frequency instability, which is a major problem in resource-constrained applications. The contribution of this paper is the advocacy of a new perspective of flexible clocking. This ideology is gradually developed in this paper as the argument is carried out through examples of novel architectures enabled by TAF-DPS. The perspective naturally emerges from the collective effect of those novel architectures. The large number of emerging applications, exemplified by edge computing and IoT, inspire system-level innovations that inevitably present new challenges to circuitlevel. Those challenges are so demanding that they require overhaul in our circuit design philosophy. This new perspective is such an overhaul in fundamental level. Its aim is to answer the challenges, for better serving the emerging demands in higher levels.

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A Power-Efficient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain

Cited by 11 publications

References 33 publications

Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial

Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial

A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <−54-dBc Spurs Under 50-mVpp Supply Ripple

A New Perspective of Flexible Clocking Ideology for Driving and Devising Circuits in Emerging Resource-Constrained Applications

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