A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm

Ito, Megumi; O’Hara, Maureen

doi:10.1109/coolchips.2016.7503681

Cited by 24 publications

(16 citation statements)

References 6 publications

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“…However, no source code is given. Other FPGA implementations were explored in [15], [16], [17], [18], [19], and [20]. GPU solutions include [21] and [22].…”

Section: B Hardware Accelerationmentioning

confidence: 99%

Acceleration of the Pair-HMM forward algorithm on FPGA with cloud integration for GATK

Wertenbroek

Thoma

2019

2019 IEEE International Conference on Bioinformatics and Biomedicine (BIBM)

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The Pair-HMM forward-algorithm is an essential algorithm found in many genomic related analyses. The high number of floating point operations in the algorithm makes it one of the main contributors to the compute time of analysis pipelines. To speed-up computations we propose an FPGA based hardware accelerator for the Amazon AWS F1 Cloud platform. The accelerator is open source and has been tested within the popular Genomic Analysis Toolkit (GATK) pipeline. The accelerator achieved up to 15× speed-up against the software implementation when used in-pipeline. The accelerator has also been tested in the experimental Spark (distributed) version of the GATK HaplotypeCaller tool. An in-depth analysis of the compute time contributions allowed to point out the main bottlenecks for accelerators in the GATK pipeline, resulting in a hybrid CPU-FPGA solution to best exploit both resources.

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“…However, no source code is given. Other FPGA implementations were explored in [15], [16], [17], [18], [19], and [20]. GPU solutions include [21] and [22].…”

Section: B Hardware Accelerationmentioning

confidence: 99%

Acceleration of the Pair-HMM forward algorithm on FPGA with cloud integration for GATK

Wertenbroek

Thoma

2019

2019 IEEE International Conference on Bioinformatics and Biomedicine (BIBM)

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“…Research on increasing the speed of PFA by optimizations and acceleration can be found in In addition, [13] and [14] propose FPGA-based implementations of PFA on the Convey Computer platform and the IBM POWER8 platform, respectively. [13] employs a systolic array to map the algorithm on FPGAs.…”

Section: B Related Workmentioning

confidence: 99%

“…[13] employs a systolic array to map the algorithm on FPGAs. [14] proposes pipelined PEs (processing elements) of the systolic array, in addition to using the CAPI interface of the IBM POWER8 platform, which makes the data transfer more efficient.…”

Section: B Related Workmentioning

confidence: 99%

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Exploration of alternative GPU implementations of the pair-HMMs forward algorithm

Ren

Koen

Al-Ars

2016

2016 IEEE International Conference on Bioinformatics and Biomedicine (BIBM)

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In order to handle the massive raw data generated by next generation sequencing (NGS) platforms, GPUs are widely used by many genetic analysis tools to speed up the used algorithms. In this paper, we use GPUs to accelerate the pair-HMMs forward algorithm, which is used to calculate the overall alignment probability in many genomics analysis tools. We firstly evaluate two different implementation methods to accelerate the pair-HMMs forward algorithm according to their effectiveness on GPU platforms. Based on these two methods, we present several implementations of the pair-HMMs forward algorithm. We execute these implementations on the NVIDIA Tesla K40 card using different datasets to compare the performance. Experimental results show that the intra-task implementation has the highest throughput in most cases, achieving pure computational throughput as high as 23.56 GCUPS for synthetic datasets. On a real dataset, the inter-task implementation achieves 4.82x speedup compared with a vectorized implementation executed on a 20-core POWER8 system.

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“…This interface hides from the users the complexities of caching and communications by allowing the user-designed accelerators to access the system memory by simple load and store requests [4]. Different workloads have been accelerated by researchers using CAPI-enabled FPGAs, including genomics algorithms [5,6], matrix algebra [7], and graph processing [8]. Furthermore, several commercial and special-purpose FPGA and ASIC-based CAPI accelerators are now being developed by different companies for the OpenPOWER platform [9].…”

Section: Ibm's Coherent Accelerator Processor Interface (Capi)mentioning

confidence: 99%

Emerging Accelerator Platforms for Data Centers

Özdal

2018

IEEE Des. Test

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Today's server architectures are designed considering the needs of a wide range of applications. For example, superscalar processors include complex control logic for out of order execution to extract instruction-level parallelism (ILP) from arbitrary programs. However, not all workloads utilize the features of a superscalar processor effectively. For example, a workload that exhibits a regular execution pattern (e.g. a dense linear algebra kernel) may not require the expensive ILP control logic for parallelism. Instead, it can be run on a throughput-oriented architecture with thousands of simple cores, such as a GPU, which can lead to much better performance and power efficiency. On the other hand, only a limited class of data-parallel applications can utilize the high throughputs provided by such architectures. As a matter of fact, existing CPU and GPU platforms may not be the most efficient choices for the compute patterns of a wide range of applications.For big data workloads, access to data is typically at least as important bottleneck as computation. The memory subsystems of today's CPU architectures are optimized for workloads that have reasonable data access locality. CPU cache hierarchies include different sizes of caches, which help capture different levels of access localities in different applications. However, if an application exhibits very little or no locality, the data access operations become inefficient for these architectures.As an example, let us consider graph applications that run on very large and unstructured datasets. Typically, the data of a vertex is computed/updated based on the data of its neighbors. In an unstructured graph, the neighbors of a vertex are stored in memory locations that may be far from each other. So, traversing the neighbors of a vertex may involve a random memory access per neighbor. If the graph is large enough so that it does not fit into the last level cache (LLC), each access to a neighbor's data may require a random DRAM access, which is typically hundreds of clock cycles. However, existing CPU architectures are not optimized for frequent random DRAM accesses. For example, each Intel Haswell Xeon core has 10 line-fill-buffers (LFBs), which means that each core can handle at most 10 L1 cache misses at a given time. However, an off-chip DRAM latency of hundreds of cycles requires hundreds of outstanding memory requests to be able to utilize the full DRAM bandwidth available in the system [1]. It was reported that 10 or more Xeon cores were needed for various graph applications to fully utilize the available DRAM bandwidth [2]. Furthermore, due to the low compute to memory-access ratios in graph applications, these cores are frequently stalled while waiting for data from off-chip memory. This leads to high power consumption by 10+ superscalar cores while not doing useful work. It was shown that custom architectures that target such communication patterns have the potential to improve power efficiency by a factor of 50x or more compared to the general-purpose CPU...

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A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm

Cited by 24 publications

References 6 publications

Acceleration of the Pair-HMM forward algorithm on FPGA with cloud integration for GATK

Acceleration of the Pair-HMM forward algorithm on FPGA with cloud integration for GATK

Exploration of alternative GPU implementations of the pair-HMMs forward algorithm

Emerging Accelerator Platforms for Data Centers

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