A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation

Abstract

Abstract-Razor is a hybrid technique for dynamic detection and correction of timing errors. A combination of error detecting circuits and micro-architectural recovery mechanisms creates a system that is robust in the face of timing errors, and can be tuned to an efficient operating point by dynamically eliminating unused timing margins. Savings from margin reclamation can be realized as per device power-efficiency improvement, or parametric yield improvement for a batch of devices. In this paper, we apply Razor to a 32 bit ARM processor with a micro-architecture design that has balanced pipeline stages with critical memory access and clock-gating enable paths. The design is fabricated on a UMC 65 nm process, using industry standard EDA tools, with a worst-case STA signoff of 724 MHz. Based on measurements on 87 samples from split-lots, we obtain 52% power reduction for the overall distribution at 1 GHz operation. We present error rate driven dynamic voltage and frequency scaling schemes where runtime adaptation to PVT variations and tolerance of fast transients is demonstrated. All Razor cells are augmented with a sticky error history bit, allowing precise diagnosis of timing errors over the execution of test vectors. We show potential for parametric yield improvement through energy-efficient operation using Razor.Index Terms-Adaptive design, dynamic voltage and frequency scaling, energy-efficient circuits, parametric yield, variation tolerance.

Timing monitoring paths selection for wide voltage IC

“…Recently, on-chip timing monitors and adaptive voltage scaling (AVS) circuits [1,2,3,4,5,6,7,8,9, 10] had been proposed to reduce the design-time margin caused by severe PVT (Process, Voltage, and Temperature) variations, such as error detection and correction techniques of Razor [1,10], ARM error detection [2], Razor-lite [3], Bubble Razor [4] and improved monitor [8], as well as errorprediction techniques of Canary Flip-flop [5], HEPP [6] and replica circuits in reconfigurable devices [9]. They use timing monitors to detect or predict timing errors, and then adaptively tune the supply voltage accordingly to reduce power.…”

Light-weight one-cycle timing error correction based on hardware software co-design

“…The in-situ error detection and correction (EDAC) techniques [4,5,6,7,8,9,10,11,12,13] are proposed to eliminate the timing margins. They monitor timing violations by specially designed circuits, and then take measures to recover functionality of the design if such a violation occurs.…”

An improved timing monitor for deep dynamic voltage scaling system

“…However, the currently used DVS methods cannot decrease the supply voltage to the best, because sufficient timing and voltage margins are reserved to resist the impact of environmental variations, transistor model inaccuracy, and EDA tool limitation, etc. [1,2,3,4,5,6].…”

“…Razor [2,3] is a kind of error detection flip-flop used to eliminate excess timing margins through real-time detection of chip operations. Microprocessors with several pipeline stages can be redesigned for low power by combining error detection and micro-architectural recovery mechanisms [2,4,5,6].…”

“…Microprocessors with several pipeline stages can be redesigned for low power by combining error detection and micro-architectural recovery mechanisms [2,4,5,6]. However, these methods are usually closely dependent on the chip architecture.…”