A power and resolution adaptive flash analog-to-digital converter

Yoo, Jincheol; Lee, Daegyu; Choi, Kyusun; Kim, Jong-Soo

doi:10.1145/566408.566468

Cited by 28 publications

(3 citation statements)

References 8 publications

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“…A transient analysis of ADC has been performed using a ramp input for different combinations of control inputs R1 and R0. The digital outputs were obtained correctly, indicating that ADC was functionally correct for different resolutions [4].…”

Section: A Functional Simulationmentioning

confidence: 78%

Design of Resolution Adaptive TIQ Flash ADC using AMS 0.35μm technology

Rajashekar

Bhat

2008

2008 International Conference on Electronic Design

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This paper presents a Resolution Adaptive Flash A/D Converter design and its performance. To achieve high speed, the proposed A/D converter utilizes Threshold Inverter Quantization technique replacing conventional analog comparators with digital comparators. The replacement results in a faster digital conversion and a reduction of the analog nodes in the ADC. The proposed ADC is a true variable resolution ADC, operates at 3-bit, 4-bit, 5-bit and 6-bit precision depending on control inputs. The proposedADC is designed with AMS 0.35µm CMOS technology and 3.3V power supply voltage and a prototype chip is fabricated. Simulation results and test results are presented.

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Section: A Functional Simulationmentioning

confidence: 78%

Design of Resolution Adaptive TIQ Flash ADC using AMS 0.35μm technology

Rajashekar

Bhat

2008

2008 International Conference on Electronic Design

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“…Thus the flash ADC is made reconfigurable to be used both as the UWB ADC, and in the multibit quantizer in the BT Σ∆ ADC. The idea of reconfiguration in flash ADCs has previously been proposed in [9], [10].…”

Section: Adc Design and Reconfigurationmentioning

confidence: 99%

Behavioral Modeling of a Programmable UWB/Bluetooth ADC

Martin¹,

Gustafsson²,

Rusu³

et al. 2007

2007 14th IEEE International Conference on Electronics, Circuits and Systems

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This paper presents the system level design of a programmable ADC that can cover the bandwidth-accuracy space of UWB and Bluetooth standards by employing a capacitive interpolation flash ADC and a sigma-delta ADC. The system level performance of the ADC architectures has been evaluated, and circuit level specifications have been established, considering the most critical circuit non-idealities. The behavioral simulation results show that the ADC can achieve 30 dB SINAD at 528 MSPS in UWB mode, and 86 dB SINAD at 1 MSPS in Bluetooth mode.

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“…A power and Resolution Adaptive Flash Analog-to-Digital Converter (PRA-ADC) enables exponential power reduction with linear resolution reduction [6]. Unused parallel voltage comparators are switched to standby mode.…”

Section: Introductionmentioning

confidence: 99%