A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing

Miyakoshi, Junichi; Murachi, Yuichiro; Hamamoto, Masaki; Iinuma, Toshitaka; Ishihara, Tomokazu; Kawaguchi, Hiroshi; Yoshimoto, Masahiko; Matsuno, Takahiro

doi:10.1109/vlsisoc.2006.313232

Cited by 4 publications

(1 citation statement)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Here, RAMs which can read out successive pixel data either on horizontal line or on vertical line at a cycle are required as SWRAM and TBRAM in order to transfer pixels data to the SIMD/SA. The custom SRAM was tailored for search window buffer and template buffer [9]. Figure 14 shows configuration of the RAM and data mapping.…”

Section: D-ds Implementation With Samentioning

confidence: 99%

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture

Miyakoshi¹,

Murachi²,

Matsuno³

et al. 2006

IEICE Transactions on Fundamentals of Electronics, Communicatio

View full text Add to dashboard Cite

We propose a sub-mW H.264 baseline-profile motion estimation processor for portable video applications. It features a VLSIoriented block partitioning strategy and low-power SIMD/systolic-array datapath architecture, where the datapath can be switched between an SIMD and systolic array depending on processing flow. The processor supports all the seven kinds of block modes, and can handle three reference frames for a CIF (352 × 288) 30-fps to QCIF (176 × 144) 15-fps sequences with a quarter-pixel accuracy. It integrates 3.3 million transistors, and occupies 2.8×3.1 mm 2 in a 130-nm CMOS technology. The proposed processor achieves a power of 800 µW in a QCIF 15-fps sequence with one reference picture.

show abstract

Section: D-ds Implementation With Samentioning

confidence: 99%