2013
DOI: 10.1016/j.tsf.2012.11.085
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A possible way to reduce absorber layer thickness in thin film CdTe solar cells

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Cited by 27 publications
(12 citation statements)
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“…In addition, the influence of film thickness on physical properties of polycrystalline CdTe thin films deposited on glass and indium tin oxide (ITO) substrates by thermal vacuum evaporation technique have been investigated [15]. Krishnakumar et al also have reported deposition of CdTe layer to reduce the CdTe thin film thickness below 1 lm using close spaced sublimation technique and substrate temperature changed [16]. Salavei et al also studied the physical and electrical properties of CdTe films deposited with different thicknesses by vacuum evaporation, and also investigated the effect of CdTe thickness on efficiency of CdTe solar cells [17].…”
Section: Introductionmentioning
confidence: 99%
“…In addition, the influence of film thickness on physical properties of polycrystalline CdTe thin films deposited on glass and indium tin oxide (ITO) substrates by thermal vacuum evaporation technique have been investigated [15]. Krishnakumar et al also have reported deposition of CdTe layer to reduce the CdTe thin film thickness below 1 lm using close spaced sublimation technique and substrate temperature changed [16]. Salavei et al also studied the physical and electrical properties of CdTe films deposited with different thicknesses by vacuum evaporation, and also investigated the effect of CdTe thickness on efficiency of CdTe solar cells [17].…”
Section: Introductionmentioning
confidence: 99%
“…10 The research group of Prof. Jaegermann have proposed that the ultrathin films with deposited CdTe double layers in two different temperatures could obtain pinhole free and higher efficiencies. 11 The second thinnest CdTe layer deposited at a low temperature fills the grain boundaries of the first one and helps to avoid formation of pinholes and shunting. For 0.5 and 0.8 lm CdTe layer, the efficiencies of g = 5.2% and 9.5% were obtained still suffering from low open-circuit voltage, V oc = 0.42 and 0.56 V. The authors ignored preforming materials profiling (i.e., by SIMS); thus, the interlayer thickness is unclear.…”
Section: Introductionmentioning
confidence: 99%
“…9 To avoid possible errors arising from a complicated highefficiency CdTe device structure, we used the standard layer stack (glass/TCO/CdS/CdTe) and preparation conditions which are well known to the CdTe community. Therefore, reference cell efficiency reported in this manuscript is limited.…”
Section: Methodsmentioning
confidence: 99%