A plastic packaged 10 Gb/s BiCMOS clock and data recovering 1:4-demultiplexer with external VCO

Hauenschild, J.; Dorschky, C.; vonMohrenfels, T. Winkler; Seitz, R.

doi:10.1109/4.545832

Cited by 34 publications

(4 citation statements)

References 13 publications

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“…The sampling circuit acts as phase detector and 1:2 demultiplexer simultaneously. This half-bit-rate architecture of the CDR/ DEMUX IC is based on the concept reported in [6] and has already realized in our previous work [7]. The combination Fig.…”

Section: Receiver Architecturementioning

confidence: 99%

2.5-Gb/s low-jitter low-power monolithically integrated optical receiver

Chen

Wang

Zhang

et al. 2011

Analog Integr Circ Sig Process

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A high-scale integrated optical receiver including a preamplifier, a limiting amplifier, a clock and data recovery (CDR) block, and a 1:4 demultiplexer (DEMUX) has been realized in a 0.25 lm CMOS technology. Using the loop parameter optimization method and the low-jitter circuit design technique, the rms and peak-topeak jitter of the recovered 625-MHz clock are 9.4 and 46.3 ps, respectively, which meet the jitter specifications stipulated in ITU-T recommendation G.958. The recovered and frequency divided 625 MHz clock has a phase noise of -83.8 dBc/Hz at 20 kHz offset in response to 2.5 Gb/s PRBS input data (2 23 -1), and the 2.5 Gb/s PRBS data has been demultiplexed into four 625 Mb/s data. The power dissipation is only 0.3 W under a single 3.3 V supply (excluding output buffers).

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Section: Receiver Architecturementioning

confidence: 99%

2.5-Gb/s low-jitter low-power monolithically integrated optical receiver

Chen

Wang

Zhang

et al. 2011

Analog Integr Circ Sig Process

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show abstract

“…The sampling circuit acts as phase detector and 1:2 demultiplexer simultaneously. This half-bit-rate architecture of the CDR/DEMUX IC is based on the concept reported in [7] and has already realized in our previous work [8]. The combination of the PD and the 1:2 DEMUX adopts a 1.25 GHz half-bit-rate clock provided by VCO.…”

Section: Receiver Architecturementioning

confidence: 99%

A low-jitter low-power monolithically integrated optical receiver for SDH STM-16

Chen

Wang

Zhang

2011

Sci. China Inf. Sci.

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A high-scale integrated optical receiver including a preamplifier, a limiting amplifier, a clock and data recovery (CDR) block, and a 1:4 demultiplexer (DEMUX) has been realized in a 0.25 µm CMOS technology. Using the loop parameter optimization method and the low-jitter circuit design technique, the rms and peak-topeak jitter of the recovered 625 MHz clock are 9.4 and 46.3 ps, respectively, which meet the jitter specifications stipulated in ITU-T recommendation G.958. In response to 2.5 Gb/s PRBS input data (2 23 −1), the recovered and frequency divided 625 MHz clock has a phase noise of −83.8 dBc/Hz at 20 kHz offset and the 2.5 Gb/s PRBS data has been demultiplexed into four 625 Mb/s data. The power dissipation is only 0.3 W under a single 3.3 V supply (excluding output buffers).

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“…This requires an oscillator which provides quadrature (I/Q) signals. The availability of quadrature signals also allows the construction of half-rate DCR architectures [3]. Half-rate DCR circuits operate at half the frequency of the incoming data rate.…”

Section: Introductionmentioning

confidence: 99%

A 9.8-11.5-GHz quadrature ring oscillator for optical receivers

Tang

Kasperkovitz

Roermund

2002

IEEE J. Solid-State Circuits

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A plastic packaged 10 Gb/s BiCMOS clock and data recovering 1:4-demultiplexer with external VCO

Cited by 34 publications

References 13 publications

2.5-Gb/s low-jitter low-power monolithically integrated optical receiver

2.5-Gb/s low-jitter low-power monolithically integrated optical receiver

A low-jitter low-power monolithically integrated optical receiver for SDH STM-16

A 9.8-11.5-GHz quadrature ring oscillator for optical receivers

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