A Pipelined 2D Transform Architecture Supporting Mixed Block Sizes for the VVC Standard

Fan, Yibo; Zeng, Yixuan; Sun, Heming; Katto, Jiro; Zeng, Xiaoyang

doi:10.1109/tcsvt.2019.2934752

Cited by 28 publications

(25 citation statements)

References 18 publications

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“…We present a unified transform architecture that can realize IDCT-II/IDST-VII/IDCT-VIII for transform unit of order 4,8,16,32 and 64 with a fixed throughput of 2 pixels per cycle. Practically, up to 80.5% of area can be reduced compared to [11] and up to 76.7% compared to [6]. In term of ALMs, we provide 92.7% reduction compared to implementation proposed by Kammoun et al in [10].…”

Section: Resultsmentioning

confidence: 85%

“…For comparison, Table 3 lists the key performance of state-of-the-art ASIC and FPGA-based works, including the VVC-MTS related works [11,9,6,10]. Gate count is the logical calculation part and it can be seen from Table 3 that compared with implementations of Fan et al [11] and Mert et al [6], our solution has obvious advantages. We present a unified transform architecture that can realize IDCT-II/IDST-VII/IDCT-VIII for transform unit of order 4,8,16,32 and 64 with a fixed throughput of 2 pixels per cycle.…”

Section: Resultsmentioning

confidence: 99%

“…However, currently, no implementation have been found for the IDCT-II of order 64. Although, [11] and [10] supports 2D for all transform types, the transform could be achieved only up to the 32×32 block size.…”

Section: Resultsmentioning

confidence: 99%

“…Although it includes 2-D implementation, blocks of sizes 64 × 64 are also not supported. Authors in [11] proposed a 2D hardware architecture for DCT-VIII and DST-VII of VVC. They implement all DST-VII DCT-VIII transform sizes using adders and shifts.…”

Section: Existing Hardware Implementationsmentioning

confidence: 99%

“…Comparison of different hardware transform designsSolutionsFan et al[11] Garrido et al[9] Mert et al[6] Kammoun et al…”

mentioning

confidence: 99%

See 4 more Smart Citations

Lightweight Hardware Implementation of VVC Transform Block for ASIC Decoder

Farhat

Hamidouche

Grill

et al. 2020

ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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Versatile Video Coding (VVC) is the next generation video coding standard expected by the end of 2020. Compared to its predecessor, VVC introduces new coding tools to make compression more efficient at the expense of higher computational complexity. This rises a need to design an efficient and optimised implementation especially for embedded platforms with limited memory and logic resources. One of the newly introduced tools in VVC is the Multiple Transform Selection (MTS). This latter involves three Discrete Cosine Transform (DCT)/Discrete Sine Transform (DST) types with larger and rectangular transform blocks. In this paper, an efficient hardware implementation of all DCT/DST transform types and sizes is proposed. The proposed design uses 32 multipliers in a pipelined architecture which targets an ASIC platform. It consists in a multi-standard architecture that supports the transform block of recent MPEG standards including AVC, HEVC and VVC. The architecture is optimized and removes unnecessary complexities found in other proposed architectures by using regular multipliers instead of multiple constant multipliers. The synthesized results show that the proposed method which sustain a constant throughput of two pixels/cycle and constant latency for all block sizes can reach an operational frequency of 600 Mhz enabling to decode in real-time 4K videos at 48 fps.

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Section: Resultsmentioning

confidence: 85%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Existing Hardware Implementationsmentioning

confidence: 99%

“…Comparison of different hardware transform designsSolutionsFan et al[11] Garrido et al[9] Mert et al[6] Kammoun et al…”

mentioning

confidence: 99%

See 3 more Smart Citations

Lightweight Hardware Implementation of VVC Transform Block for ASIC Decoder

Farhat

Hamidouche

Grill

et al. 2020

ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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show abstract

Study on versatile video coding multiple transform selection of hardware architecture based on FPGA

Zhang

Shi

Zhang

2022

Multimed Tools Appl

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Multiple Transform Selection Concept Modeling and Implementation Using Dynamic and Parameterized Dataflow Graphs

Haggui¹,

Belghith

Hamidouche

et al. 2022

J Sign Process Syst

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The new video coding standard, Versatile Video Coding (VVC), released by the end of 2020 has increased the coding complexity both at encoder and decoder sides. This complexity increase is due to several coding tools proposed to enhance the coding efficiency. One of these tools is the Multiple Transform Selection (MTS) concept, a new approach for the transform unit. This paper aims at providing a new optimization of the MTS based on dataflow modeling. The proposed approach takes benefit of the different parallelism levels of the MTS in order to create an optimized multicore implementation. Also, this paper study the impact of the dataflow model granularity and the dynamic reconfiguration on the implementation efficiency on x86 multicore architectures. The PREESM tool is used in this study to develop the proposed dataflow models and for the granularity analysis. The dynamic reconfiguration study is here performed using the SPIDER

show abstract

A Pipelined 2D Transform Architecture Supporting Mixed Block Sizes for the VVC Standard

Cited by 28 publications

References 18 publications

Lightweight Hardware Implementation of VVC Transform Block for ASIC Decoder

Lightweight Hardware Implementation of VVC Transform Block for ASIC Decoder

Study on versatile video coding multiple transform selection of hardware architecture based on FPGA

Multiple Transform Selection Concept Modeling and Implementation Using Dynamic and Parameterized Dataflow Graphs

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