A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs

Rai, Shubham; Rupani, Ansh; Walter, Dennis; Raitza, Michael; Heinzig, André; Baldauf, Tim; Trommer, Jens; Mayr, Christian; Weber, Walter M.; Kumar, Akash

doi:10.23919/date.2018.8342080

Cited by 27 publications

(10 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…. Experiments using our physical synthesis flow show that SiNW RFETs based circuits for MCNC benchmarks occupy just 17.43% more area as compared to their CMOS counterparts [41]. Even thought the average area is more than CMOS baseline, the results are very encouraging considering the fact that in the used lab-technology, the individual RFETs are almost twice the size of CMOS.…”

Section: Area Resultsmentioning

confidence: 82%

“…Recently, majority logic was proposed as the natural abstraction for newer nanotechnology and this forms the basis for new majority inverter graph (MIG) synthesis flow [3]. An area optimizing technology mapping flow exploiting functionally enhanced logic gates [56] was proposed in [41]. The authors incorporated inverter minimization to have more area savings specially designed for silicon nanowires FETsbased logic gates.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Emerging reconfigurable nanotechnologies

Rail

Srinivasa

Cadareanu

et al. 2018

Proceedings of the International Conference on Computer-Aided Design

Self Cite

View full text Add to dashboard Cite

Several emerging reconfigurable technologies have been explored in recent years offering device level runtime reconfigurability. These technologies offer the freedom to choose between p-and n-type functionality from a single transistor. In order to optimally utilize the feature-sets of these technologies, circuit designs and storage elements require novel design to complement the existing and future electronic requirements. An important aspect to sustain such endeavors is to supplement the existing design flow from the device level to the circuit level. This should be backed by a thorough evaluation so as to ascertain the feasibility of such explorations. Additionally, since these technologies offer runtime reconfigurability and often encapsulate more than one functions, hardware security features like polymorphic logic gates and on-chip key storage come naturally cheap with circuits based on these reconfigurable technologies. This paper presents innovative approaches devised for circuit designs harnessing the reconfigurable features of these nanotechnologies. New circuit design paradigms based on these nano devices will be discussed to brainstorm on exciting avenues for novel computing elements.

show abstract

Section: Area Resultsmentioning

confidence: 82%

Section: Introductionmentioning

confidence: 99%

Emerging reconfigurable nanotechnologies

Rail

Srinivasa

Cadareanu

et al. 2018

Proceedings of the International Conference on Computer-Aided Design

Self Cite

View full text Add to dashboard Cite

show abstract

“…1D RFETs are more mature as compared to 2D devices due to their similarity to CMOS manufacturing process [52,53,54]. The stacked nanowire or nanosheet geometry is also considered as a successor to the FinFET geometry that is promoted to be used at lower technology nodes [55].…”

Section: A Reconfigurable Nanotechnologiesmentioning

confidence: 99%

“…At the logical abstraction, the runtime-reconfigurable properties offered by RFETs can be used to build logic gates with extended functionality [61,52,57,62,63]. These logic gates can be configured to deliver different logic functionalities on application of an external potential.…”

Section: B Polymorphic Logic Gates and Logic Lockingmentioning

confidence: 99%

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?

Rai

Garg

Pilato

et al. 2021

2021 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

Self Cite

View full text Add to dashboard Cite

With the advent of 5G and IoT applications, there is a greater thrust in terms of hardware security due to imminent risks caused by high amount of intercommunication between various subsystems. Security gaps in integrated circuits, thus represent high risks for both-the manufacturers and the users of electronic systems. Particularly in the domain of Intellectual Property (IP) protection, there is an urgent need to devise security measures at all levels of abstraction so that we can be one step ahead of any kind of adversarial attacks. This work presents IP protection measures from multiple perspectives-from systemlevel down to device-level security measures, from discussing various attack methods such as reverse engineering and hardware Trojan insertions to proposing new-age protection measures such as multi-valued logic locking and secure information flow tracking. This special session will give a holistic overview at the current state-of-the-art measures and how well we are prepared for the next generation circuits and systems.1 Not requiring any changes to the EDA flows.

show abstract

“…In order to circumvent CMOS scaling and the various challenges that come with it, researchers have proposed many architectural modifications and system-level techniques which either focus on a single metric like area, power and delay or a particular combination of them. Many take a fresh perspective by involving emerging technologies like memristors [37,40,21], spintronics [65] and controllable-polarity transistors based on materials like silicon [30,31,64,66] and germanium [62] nanowires, carbon nanotubes [11] and 2D materials like WSe 2 [52]. Nikonov et al [48] demonstrate the promises of beyond-CMOS devices by benchmarking them and helping researchers seek methods of improving their power versus performance.…”

Section: Introductionmentioning

confidence: 99%

A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies

et al. 2021

Self Cite

View full text Add to dashboard Cite

The functional component for an FPGA is the logic element which enables it to adapt to various hardware descriptions. This behavior is mostly due to the MUX-like functional flexibility provided by these logic elements or cells. However, in recent years, decelerating transistor sizing as per Moore's law has led to diminishing power, area and delay returns over cost [22]. Hence, the idea of venturing into FPGA logic cell designs based on emerging technologies is becoming not merely attractive, but even inescapable. The present work surveys various conventional and non-conventional logic cell designs proposed in the literature by identifying four logic design families, namely LUT-based, cone-based, matrix/cluster-based and transistor array-based. We then carry out a detailed comparison at two levels -a quantitative comparison based on metrics like power, delay and area which govern the overall performance of various FPGA architectures and secondly a qualitative comparison on factors which are important considering the ease of mainstream adoption. We highlight the importance of introducing and co-optimizing novel devices and architectures to maximize the overall FPGA performance.

show abstract

A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs

Cited by 27 publications

References 13 publications

Emerging reconfigurable nanotechnologies

Emerging reconfigurable nanotechnologies

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?

A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies

Contact Info

Product

Resources

About