2021
DOI: 10.1109/ted.2020.3045960
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A Physical Model for Bulk Gate Insulator Trap Generation During Bias-Temperature Stress in Differently Processed p-Channel FETs

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Cited by 21 publications
(1 citation statement)
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“…Additionally, interface traps resulting from defects at the nanosheet-shell interfaces are another source of variability. These traps can adversely affect device characteristics, including mobility degradation and threshold voltage instability [11][12][13] . Therefore, understanding the nature and impact of these D2D variabilities is imperative to improve the performance and reliability of advanced NSFETs.Notably, an alternative structural design for NSFET, that is, core-insulator-embedded NSFET (C-NSFETs), has been proposed recently 14 .…”
mentioning
confidence: 99%
“…Additionally, interface traps resulting from defects at the nanosheet-shell interfaces are another source of variability. These traps can adversely affect device characteristics, including mobility degradation and threshold voltage instability [11][12][13] . Therefore, understanding the nature and impact of these D2D variabilities is imperative to improve the performance and reliability of advanced NSFETs.Notably, an alternative structural design for NSFET, that is, core-insulator-embedded NSFET (C-NSFETs), has been proposed recently 14 .…”
mentioning
confidence: 99%