A physical method to incorporate parasitic elements in a circuit simulator based on the partial inductance concept

Abstract

-In switching Power Electronics circuits inductive parasitics of wiring and components contribute substantially to the current and voltage waveforms. This article addresses the theoretical basis as well as the implementation and validation of the incorporation of these inductances in a computerised circuit simulation. The program presented in this paper is using the same formulas as INCAm. It differs from INCAm especially in that it generates code that can immediately be given to a circuit-simulator, to perform a time-simulation.

Pogo Pin Parasitic Impedance Characterisation and Influence on Pmic Semiconductor Evaluation Proces

“…6, real design model of Buck convertor output stage was used, consists of pair of MOSFET transistors and the driver circuit, simulating pulse width modulation process. On the source side of P-MOS transistor, we added small 2nH inductance [7] that represents real value of Pogo-pin parasitic inductance. Output inductor was simulated by the ideal inductor in serial with small resistor representing parasitic resistance.…”

Combined ZVS–ZCS topology for high-current direct current hybrid switches: design aspects and first measurements

“…Using (2), this results in a di/dt of at least 20 A ms 21 or equivalently a stray inductance smaller than 0.4 mH. Stray inductance calculations have been done with the method described in Evenblij et al [11]. Fig.…”

Improved distributed model for capacitors in high-performance packages

“…Before considering a model for inductive effects in a capacitor, it is important to note that inductance cannot be defined except for a path forming a complete loop [4]. Thus, we must consider the impedance of a closed path including a capacitor.…”