A phase-noise reduction technique for RF CMOS voltage-controlled oscillator with a series LC resonator

Oh, Nam-Jin

doi:10.1016/j.mejo.2014.02.003

Cited by 13 publications

(12 citation statements)

References 10 publications

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“…Besides, the PMOS pair adds more negative resistance to the structure and makes the output waveform more rectangular. It should be noticed that a square-wave waveform has usually a lower ISF than a sine-wave waveform [6]. Knowing the noise sources and their contribution to the generated phase noise is necessary for analyzing the phase noise.…”

Section: Structure Analysis Of Oscillatormentioning

confidence: 99%

“…The simulations indicate a low loop gain at zero-crossings points can significantly decrease the ISF at these points. Based on the mentioned investigation, we have significantly improved the ISF and the phase noise by minor changes in the proposed oscillator [6]. The phase noise reduction technique is introduced by Oh [6] in Figure 1.…”

Section: Introductionmentioning

confidence: 97%

“…Based on the mentioned investigation, we have significantly improved the ISF and the phase noise by minor changes in the proposed oscillator [6]. The phase noise reduction technique is introduced by Oh [6] in Figure 1. Low phase noise Oscillator with a series LC resonator section 2.…”

Section: Introductionmentioning

confidence: 97%

“…However, implementing methods using inductors requires much space; a new structure is proposed that utilizes a kind of filtering that just needs extra capacitors. The structure introduced in literature [6] illustrated in Figure 1. In this figure, a phase shift is created by the between the drain and the gate voltage waveform of the NMOS transistors.…”

Section: Introductionmentioning

confidence: 99%

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A Phase Noise Reduction Technique in LC Cross-coupled Oscillators with Adjusting Transistors Operating Regions

Aghabagheri

Naimi

Javadi

2020

IJE

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In this paper, an intuitive analysis of a phase noise reduction technique is done, and then a modified structure is proposed to achieve higher phase noise reduction than the original one. This method reduces the impact of noise sources on the phase noise by decreasing closed-loop gain in zero-crossings points and moving this high closed-loop gain to the non-zero-crossings points. This reduction tested on different scales and all of them showed improvement in the phase noise performance. In other words, this method reduces the phase noise by manipulating the operation region. Impulse sensitivity function (ISF) for the proposed structure shows degradation in comparison to the original structure. We have designed the proposed oscillator in 0.18 μm using CMOS TSMC standard technology. The proposed oscillator operates on 900 MHz, moreover, phase noise is-138.4 dBc/Hz at 1 MHz offset frequency while it consumes 3.11 mA from 1.8 V supply voltage.

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Section: Structure Analysis Of Oscillatormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 97%

Section: Introductionmentioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Phase Noise Reduction Technique in LC Cross-coupled Oscillators with Adjusting Transistors Operating Regions

Aghabagheri

Naimi

Javadi

2020

IJE

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“…replacing the load resistor R L with the complementary PMOS transistors. In [8], a new LMV is proposed using a SLC tank resonator instead of using a PLC tank resonator for low-phase noise design by combining a single-balanced mixer and a complementary VCO. Figure 4 shows the single-balanced LMV (SB-LMV) cell by modifying the current source as an inductive degenerated LNA and adding simple first-order RC low-pass filter (LPF).…”

Section: Circuit Design Of Db-lmvmentioning

confidence: 99%

A Single-Stage Low-Power Double-Balanced Mixer Merged with LNA and VCO

Oh¹

2017

IJECE

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This paper proposes three types of single stage low-power RF front-end, called double-balanced LMVs, by merging LNA, mixer, and voltagecontrolled oscillator (VCO) exploiting a series LC (SLC) network. The low intermediate frequency (IF) or baseband signal can be directly sensed at the drain nodes of the VCO switching transistors by adding a simple resistorcapacitor (RC) low-pass filter (LPF). By adopting a double-balanced mixer topology, the strong leakage of the local oscillator (LO) at the IF output is effectively suppressed. Using a 65 nm CMOS technology, the proposed double-balanced LMVs (DB-LMVs) are designed. Oscillating at around 2.4 GHz ISM band, the phase noise of the proposed three DB-LMVs is −111 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain is larger than 36 dB and the double-side band (DSB) noise figure (NF) is less than 7.7 dB. The DB-LMVs consume only 0.2 mW dc power from 1-V supply voltage.

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Increasing power efficiency in the design of a low power and low phase noise CMOS LC oscillator

Kebria

Ghonoodi

2020

Circuit Theory & Apps

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SummaryThis study developed a local oscillator (LO) with low phase noise and low power consumption. The proposed oscillator core comprises a pair of cross‐coupled transistors, which are fed by another pair of transistors that injects current at moments close to the peak of output voltage. The position of the current injection transistors, which are inserted in series with the cross‐coupled transistors, affects the waveform of current injected into an inductive–capacitive (LC) tank. Installing a capacitor on the source node of the cross‐coupled transistors increases the current injected into the LC tank and thereby augments the output voltage amplitude and power efficiency of the LO. The resonator phase shift and Q can be corrected by adjusting the source capacitance, which filters noise. These changes reduce the phase noise to −123.4 dBc/Hz at a frequency offset of 1 MHz and improve oscillator performance with a figure of merit equal to −193.5 dBc/Hz. To evaluate the LC tank, a 5 GHz LO was simulated at 1.8 V power supply and 2.5 mW power consumption. The simulation was conducted using a practical 0.18 complementary metal–oxide–semiconductor model manufactured by the Taiwan Semiconductor Manufacturing Company. The simulation results confirmed the analytical findings.

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A phase-noise reduction technique for RF CMOS voltage-controlled oscillator with a series LC resonator

Cited by 13 publications

References 10 publications

A Phase Noise Reduction Technique in LC Cross-coupled Oscillators with Adjusting Transistors Operating Regions

A Phase Noise Reduction Technique in LC Cross-coupled Oscillators with Adjusting Transistors Operating Regions

A Single-Stage Low-Power Double-Balanced Mixer Merged with LNA and VCO

Increasing power efficiency in the design of a low power and low phase noise CMOS LC oscillator

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