A Performance Study for Iterative Stencil Loops on GPUs with Ghost Zone Optimizations

Abstract

Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture, there are usually halo regions that need to be updated and exchanged among different processing elements (PEs). In addition, synchronization is often used to signal the completion of halo exchanges. Both communication and synchronization may incur significant overhead on parallel architectures with shared memory. This is especially true in the case of graphics processors (GPUs), which do not preserve the state of the per-core L1 storage across global synchronizations. To reduce these overheads, ghost zones can be created to replicate stencil operations, reducing communication and synchronization costs at the expense of redundantly computing some values on multiple PEs. However, the selection of the optimal ghost zone size depends on the characteristics of both the architecture and the application, and it has only been studied for message-passing systems in distributed environments. To automate this process on shared memory systems, we establish a performance model using NVIDIA's Tesla architecture as a case study and propose a framework that uses the performance model to automatically select the ghost zone size that performs best and generate appropriate code. The modeling is validated by four diverse ISL applications, for which the predicted ghost zone configurations are able to achieve a speedup no less than 95% of the optimal speedup.

High-performance code generation for stencil computations on GPU architectures

“…Recent work has shown promise for high performance by use of overlapped tiling on GPUs [11] for stencil computations. In this paper, we present an automated approach to generate efficient overlapped tiling code for stencil computations on GPUs.…”

“…Our equivalent Jacobi 2-D stencil achieves 49.5 GFlop/s in double-precision mode on the GTX 580. Meng et al [11] report approximately 2 × 10 6 cycles per iteration on a GTX 280 for a Poisson stencil that has been manually tiled using overlapped tiling with a time tile size of 3. With a clock speed of 1.3 GHz, this gives approximately 70.2 GFlop/s.…”

“…A number of recent studies have focused on optimizing stencil computations on multicore CPUs [2,6,8,17,19] as well as GPUs [11][12][13].…”

“…The standard approach to time-tiling of stencil computations requires loop skewing to make tiling legal and this results in loss of inter-tile concurrency [10], since inter-tile dependences are introduced in the spatial directions due to the skewing. The approach of "overlapped tiling" [10], also called "ghost zone" optimization [3,11], has been used for preserving concurrency in parallel time-tiled execution of stencil computations. However, we are unaware of any fully automated compiler approach for the generation of overlapped-tiling code for execution on GPUs.…”

A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices

“…In the literature, the problem of designing efficient implementations for this class of algorithms has been addressed for both CPUs ( [5], [6]) and GPGPUs ( [7], [8]): on such architectures, the main problems that have been faced are the memory organization and the data transfers.…”