A Performance Model for Run-Time Reconfigurable Hardware Accelerator

Wang, Gang; Du, Chun‐Hui; Chen, Jian; Ma, Jianliang; Chen, Tianzhou

doi:10.1007/978-3-642-03644-6_5

Cited by 3 publications

(2 citation statements)

References 15 publications

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“…The model, however, does not take into account the modeling of memory modules which must be considered in real scenarios. So me developed abstract model for a reconfigurable co mputer, [7] focused on the performance model for runtime reconfigurable hard ware accelerators. In a theoretical analysis, the factors such as speedup, commun ication and configuration overheads are considered, but this model does not consider the utilization of the accelerator in a network perspective.…”

Section: Related Workmentioning

confidence: 99%

Analysis of Reconfigurable Processors Using Petri Net

Heidari

2013

IJCNIS

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In this paper, we propose Petri net models for processing elements. The processing elements include: a general-purpose processor (GPP), a reconfigurable element (RE), and a hybrid element (combining a GPP with an RE). The models consist of many transitions and places. The model and associated analysis methods provide a promising tool for modeling and performance evaluation of reconfigurable processors. The model is demonstrated by considering a simple example. This paper describes the development of a reconfigurable processor; the developed system is based on the Petri net concept. Petri nets are becoming suitable as a formal model for hardware system design. Designers can use Petri net as a modeling language to perform high level analysis of complex processors designs processing chips. The simulation does with PIPEv4.1 simulator. The simulation results show that Petri net state spaces are bounded and safe and have not deadlock and the average of number tokens in first token is 0.9901 seconds. In these models, there are only 5% errors; also the analysis time in these models is 0.016 seconds

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Section: Related Workmentioning

confidence: 99%

Analysis of Reconfigurable Processors Using Petri Net

Heidari

2013

IJCNIS

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“…These contributions use a reconfigurable framework for the real-time multimedia dataset that describes the different entities executing in the high performance reconfigurable computing (HPRC) and Reconfigurable Register File (RRF) stack to reduce temporal isolation. This reconfiguration technique increases the system performance and also the output quality experienced by the user without any temporal deviation (Wang et al, 2009). Analytical modeling is extensively useful in performance evaluation due to its superiority and flexibility (Kant, 1992).…”

Section: Petri Net Performance Modelmentioning

confidence: 99%

Petri Net-based System Modelling for Performance Analysis of Reconfigurable Soft-core Processor using FPGA

Maheswari¹,

Pattabiraman²

2016

IJTech

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In any heterogeneous system, porting reconfigurable computing is often a high performance platform for a broad range of computationally challenging issues. However, efficiently utilizing the maximum potential of these reconfigurable systems is a difficult job without understanding their performance characteristics. This work proposes an analytic performance model using Petri Nets (PN) for a Reconfigurable OR1200 (ROR1200) soft-core processor with model validation and verifications. By modeling the ROR1200 system using Petri Nets, both behavioral and structural properties existing in parallel systems were analyzed. The Bound Level Analysis with respect to the dependency level of data is also performed on Soft Core Processors (SCP) like the ROR1200, the OR1200 and the MicroBlaze.

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