A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields

Bartolini, Sandro; Branovic, Irina; Giorgi, Roberto; Martinelli, Enrico

doi:10.1109/sbac-pad.2004.5

Cited by 13 publications

(6 citation statements)

References 6 publications

(13 reference statements)

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“…We also provide a more precise evaluation of the resistance against power analysis attacks for each design, due to the integration of an objective metric that quantifies the information leaked by different protected implementation. Lastly, our quantitative analysis applies jointly to security and performance issues and drives the process of ISE identification and synthesis; to the best of our knowledge, prior ISE identification methods have been driven primarily by performance [10,4,25].…”

Section: Background and Related Workmentioning

confidence: 99%

A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions

Regazzoni

Cevrero

Standaert

et al. 2009

Lecture Notes in Computer Science

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Abstract. Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been proposed as an alternative to CMOS. However, they should only be used sparingly, since their area and power consumption are both significantly larger than for CMOS. We propose to augment a processor, realized in CMOS, with custom instruction set extensions, designed with security and performance as the primary objectives, that are realized in a protected logic. We have developed a design flow based on standard CAD tools that can automatically synthesize and place-and-route such hybrid designs. The flow is integrated into a simulation and evaluation environment to quantify the security achieved on a sound basis. Using MCML logic as a case study, we have explored different partitions of the PRESENT block cipher between protected and unprotected logic. This experiment illustrates the tradeoff between the type and amount of application-level functionality implemented in protected logic and the level of security achieved by the design. Our design approach and evaluation tools are generic and could be used to partition any algorithm using any protected logic style.

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Section: Background and Related Workmentioning

confidence: 99%

A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions

Regazzoni

Cevrero

Standaert

et al. 2009

Lecture Notes in Computer Science

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“…Word-level polynomial multiplication was shown in [55] to be the time-critical operation when targeting an ARM processor and a special Galois Field multiplication instruction resulted in significant performance improvement. Instruction set extensions targeting a SPARC V8 processor core were used to accelerate the multiplication of binary polynomials for arithmetic in GF(2 m ) in [56], resulting in almost double the performance for the Galois Field GF (2 191 ) and a fixed reduction polynomial.…”

Section: Previous Workmentioning

confidence: 99%

Fast and Efficient Implementation of AES via Instruction Set Extensions

Elbirt

2007

21st International Conference on Advanced Information Networking and Applications Workshops (AINAW'07)

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Efficient implementation of block ciphers is critical towards achieving both high security and high-speed processing. Numerous block ciphers, including the Advanced Encryption Standard (AES), have been proposed and implemented, using a wide and varied range of functional operations. Existing microprocessor architectures do not provide this broad range of support. However, the advent of intellectual property (IP) processor cores presents the opportunity to augment existing datapaths with instruction set extensions to add acceleration modules in the form of new instructions. We will present a general purpose instruction set extension to a 32-bit SPARC V8 compatible processor core that accelerates the performance of Galois Field fixed field constant multiplication, a core element of the AES algorithm. This extension will be shown to accelerate AES encryption versus pure software implementations at a small hardware cost. This matches the improvement demonstrated in previously proposed AES-specific instruction set extensions while maintaining a generalized implementation format capable of supporting other algorithms that use Galois Field fixed field constant multiplication.

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“…Instruction sets proposed by [9], [10] and [11] provide for multiplication and reversing the bits of the field element. These experiments demonstrated that finite field multiplication consumes more than 90% of elliptical curve software benchmarks.…”

Section: Introductionmentioning

confidence: 99%

Acceleration of finite field arithmetic algorithms in embedded processing platforms utilizing instruction set extensions

Jachimiec

Martinez-Vallina

Saniie

2007

2007 IEEE International Conference on Electro/Information Technology

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Finite field arithmetic is essential to error correction and cryptography.Instruction set extensions are an alternative to ASICs and DSPs while providing the same performance with embedded CPUs. An instruction set extension is presented that handles various fields in GF(2 m ). A MIPS DLX processor core is accelerated using an auxiliary processing interface to a finite field arithmetic unit. Additional instructions are added to the DLX core set which are used to create finite field arithmetic benchmarks.The processor core and extensions datapath are synthesized in a standard cell 0.18µm CMOS process achieving a 233MHz clock. The combined DLX and FFU system demonstrates a 355× speed-up when performing elliptical curve projective point doubling in GF(2 163 ).

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A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields

Abstract: Abstract

Cited by 13 publications

References 6 publications

A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions

A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions

Fast and Efficient Implementation of AES via Instruction Set Extensions

Acceleration of finite field arithmetic algorithms in embedded processing platforms utilizing instruction set extensions

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